2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
5 ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
7 ## This program is free software; you can redistribute it and/or
8 ## modify it under the terms of the GNU General Public License as
9 ## published by the Free Software Foundation; version 2 of
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 chip northbridge/intel/i945
25 device lapic_cluster 0 on
26 chip cpu/intel/socket_mFCPGA478
31 device pci_domain 0 on
32 device pci 00.0 on # Host bridge
33 subsystemid 0x17aa 0x2015
35 device pci 01.0 on # PCI-e
36 device pci 00.0 on # VGA
37 subsystemid 0x17aa 0x20a4
41 device pci 02.0 on # GMA Graphics controller
42 subsystemid 0x17aa 0x201a
44 device pci 02.1 on # display controller
45 subsystemid 0x17aa 0x201a
48 chip southbridge/intel/i82801gx
49 register "pirqa_routing" = "0x0b"
50 register "pirqb_routing" = "0x0b"
51 register "pirqc_routing" = "0x0b"
52 register "pirqd_routing" = "0x0b"
53 register "pirqe_routing" = "0x0b"
54 register "pirqf_routing" = "0x0b"
55 register "pirqg_routing" = "0x0b"
56 register "pirqh_routing" = "0x0b"
59 # 0 No effect (default)
60 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
61 # 2 SCI (if corresponding GPIO_EN bit is also set)
62 register "gpi13_routing" = "2"
63 register "gpi12_routing" = "2"
64 register "gpi8_routing" = "2"
66 register "sata_ahci" = "0x0"
68 register "gpe0_en" = "0x11000006"
70 device pci 1b.0 on # Audio Cnotroller
71 subsystemid 0x17aa 0x2010
73 device pci 1c.0 on # Ethernet
74 subsystemid 0x17aa 0x2001
76 device pci 1c.1 on end # WLAN
77 device pci 1d.0 on # USB UHCI
78 subsystemid 0x17aa 0x200a
80 device pci 1d.1 on # USB UHCI
81 subsystemid 0x17aa 0x200a
83 device pci 1d.2 on # USB UHCI
84 subsystemid 0x17aa 0x200a
86 device pci 1d.3 on # USB UHCI
87 subsystemid 0x17aa 0x200a
89 device pci 1d.7 on # USB2 EHCI
90 subsystemid 0x17aa 0x200b
92 device pci 1e.0 on # PCI Bridge
93 chip southbridge/ti/pci1x2x
95 subsystemid 0x17aa 0x2012
97 register "scr" = "0x0844d070"
98 register "mrr" = "0x01d01002"
102 device pci 1f.0 on # PCI-LPC bridge
103 subsystemid 0x17aa 0x2009
105 device pnp ff.1 on # dummy
108 register "backlight_enable" = "0x01"
109 register "dock_event_enable" = "0x01"
112 device pnp ff.2 on # dummy
120 register "config0" = "0xa6"
121 register "config1" = "0x05"
122 register "config2" = "0xa0"
123 register "config3" = "0x05"
125 register "beepmask0" = "0xfe"
126 register "beepmask1" = "0x96"
128 register "event2_enable" = "0xff"
129 register "event3_enable" = "0xff"
130 register "event4_enable" = "0xf4"
131 register "event5_enable" = "0x3f"
132 register "event6_enable" = "0x80"
133 register "event7_enable" = "0x01"
134 register "event8_enable" = "0x01"
135 register "event9_enable" = "0xff"
136 register "eventc_enable" = "0xff"
137 register "eventd_enable" = "0xff"
138 register "eventc_enable" = "0x3c"
140 register "wlan_enable" = "0x01"
141 register "trackpoint_enable" = "0x03"
144 chip superio/nsc/pc87382
145 device pnp 164e.2 on # IR
149 device pnp 164e.3 off # Serial Port
153 device pnp 164e.7 on # GPIO
157 device pnp 164e.19 on # DLPC
162 chip superio/nsc/pc87384
163 device pnp 2e.0 off #FDC
166 device pnp 2e.1 on # Parallel Port
171 device pnp 2e.2 off # Serial Port / IR
176 device pnp 2e.3 on # Serial Port
181 device pnp 2e.7 on # GPIO
185 device pnp 2e.a off # WDT
189 device pci 1f.1 on # IDE
190 subsystemid 0x17aa 0x200c
192 device pci 1f.2 on # SATA
193 subsystemid 0x17aa 0x200d
195 device pci 1f.3 on # SMBUS
196 subsystemid 0x17aa 0x200f