src/mainboard/lanner/em8510/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Original take from digitallogic/adl855pc
   5  *
   6  * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <stdint.h>
  24 #include <device/pci_def.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <arch/hlt.h>
  29 #include <stdlib.h>
  30 #include "pc80/udelay_io.c"
  31 #include <pc80/mc146818rtc.h>
  32 #include <console/console.h>
  33 #include "southbridge/intel/i82801dx/i82801dx.h"
  34 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
  35 #include "northbridge/intel/i855/raminit.h"
  36 #include "northbridge/intel/i855/debug.c"
  37 #include "superio/winbond/w83627thf/w83627thf_early_serial.c"
  38 #include "cpu/x86/mtrr/earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1)
  42
  43 static inline int spd_read_byte(unsigned device, unsigned address)
  44 {
  45         return smbus_read_byte(device, address);
  46 }
  47
  48 #include "northbridge/intel/i855/raminit.c"
  49 #include "northbridge/intel/i855/reset_test.c"
  50 #include "lib/generic_sdram.c"
  51
  52 void main(unsigned long bist)
  53 {
  54         static const struct mem_controller memctrl[] = {
  55                 {
  56                         .d0 = PCI_DEV(0, 0, 1),
  57                         .channel0 = { (0xa<<3)|0, 0 },
  58                 },
  59         };
  60
  61         if (bist == 0) {
  62 #if 0
  63                 enable_lapic();
  64                 init_timer();
  65 #endif
  66         }
  67
  68         w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  69         uart_init();
  70         console_init();
  71
  72         /* Halt if there was a built in self test failure */
  73         report_bist_failure(bist);
  74
  75 #if 0
  76         print_pci_devices();
  77 #endif
  78
  79         if(!bios_reset_detected()) {
  80                 enable_smbus();
  81 #if 1
  82                 dump_spd_registers(&memctrl[0]);
  83                 dump_smbus_registers();
  84 #endif
  85
  86                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
  87
  88         }
  89
  90 #if 0
  91         dump_pci_devices();
  92         dump_pci_device(PCI_DEV(0, 0, 0));
  93
  94         // Check all of memory
  95         ram_check(0x00000000, msr.lo+(msr.hi<<32));
  96         // Check 16MB of memory @ 0
  97         ram_check(0x00000000, 0x01000000);
  98         // Check 16MB of memory @ 2GB
  99         ram_check(0x80000000, 0x81000000);
 100 #endif
 101 }
 102