src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include <spd.h>
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "northbridge/amd/amdk8/debug.c"
  43 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  44 #include <usbdebug.h>
  45 #include <cpu/amd/mtrr.h>
  46 #include "cpu/x86/bist.h"
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48 #include "southbridge/amd/rs690/rs690_early_setup.c"
  49 #include "southbridge/amd/sb600/sb600_early_setup.c"
  50
  51 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54 }
  55
  56 /* called in raminit_f.c */
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 /*called in raminit_f.c */
  62 static inline int spd_read_byte(u32 device, u32 address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67 #include "northbridge/amd/amdk8/amdk8.h"
  68 #include "northbridge/amd/amdk8/incoherent_ht.c"
  69 #include "northbridge/amd/amdk8/raminit_f.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72 #include "resourcemap.c"
  73 #include "cpu/amd/dualcore/dualcore.c"
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76 #include "cpu/amd/model_fxx/fidvid.c"
  77 #include "northbridge/amd/amdk8/early_ht.c"
  78
  79 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  80 {
  81         device_t dev;
  82         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  83         int needs_reset = 0;
  84         u32 bsp_apicid = 0;
  85         msr_t msr;
  86         struct cpuid_result cpuid1;
  87         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  88
  89         if (!cpu_init_detectedx && boot_cpu()) {
  90                 /* Nothing special needs to be done to find bus 0 */
  91                 /* Allow the HT devices to be found */
  92                 enumerate_ht_chain();
  93
  94                 /* sb600_lpc_port80(); */
  95                 sb600_pci_port80();
  96         }
  97
  98         if (bist == 0) {
  99                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 100         }
 101
 102         enable_rs690_dev8();
 103         sb600_lpc_init();
 104
 105         dev=PNP_DEV(0x2e, W83627DHG_SP1);
 106         w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
 107         uart_init();
 108
 109 #if CONFIG_USBDEBUG
 110         sb600_enable_usbdebug(0);
 111         early_usbdebug_init();
 112 #endif
 113
 114         console_init();
 115
 116         /* Halt if there was a built in self test failure */
 117         report_bist_failure(bist);
 118         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 119
 120         setup_kt690_resource_map();
 121
 122         setup_coherent_ht_domain();
 123
 124 #if CONFIG_LOGICAL_CPUS==1
 125         /* It is said that we should start core1 after all core0 launched */
 126         wait_all_core0_started();
 127         start_other_cores();
 128 #endif
 129         wait_all_aps_started(bsp_apicid);
 130
 131         ht_setup_chains_x(sysinfo);
 132
 133         /* run _early_setup before soft-reset. */
 134         rs690_early_setup();
 135         sb600_early_setup();
 136
 137         /* Check to see if processor is capable of changing FIDVID  */
 138         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 139         cpuid1 = cpuid(0x80000007);
 140         if( (cpuid1.edx & 0x6) == 0x6 ) {
 141
 142                 /* Read FIDVID_STATUS */
 143                 msr=rdmsr(0xc0010042);
 144                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 145
 146                 enable_fid_change();
 147                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 148                 init_fidvid_bsp(bsp_apicid);
 149
 150                 /* show final fid and vid */
 151                 msr=rdmsr(0xc0010042);
 152                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 153
 154         } else {
 155                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 156                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 157         }
 158
 159         needs_reset = optimize_link_coherent_ht();
 160         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 161         rs690_htinit();
 162         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 163
 164         if (needs_reset) {
 165                 print_info("ht reset -\n");
 166                 soft_reset();
 167         }
 168
 169         allow_all_aps_stop(bsp_apicid);
 170
 171         /* It's the time to set ctrl now; */
 172         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 173                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 174         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 175         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 176
 177         rs690_before_pci_init();
 178         sb600_before_pci_init();
 179
 180         post_cache_as_ram();
 181 }