src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40 #include <spd.h>
  41
  42 #include "cpu/x86/lapic/boot_cpu.c"
  43 #include "northbridge/amd/amdk8/reset_test.c"
  44 #include "northbridge/amd/amdk8/debug.c"
  45 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  46
  47 #include <usbdebug.h>
  48
  49 #include <cpu/amd/mtrr.h>
  50 #include "cpu/x86/bist.h"
  51
  52 #include "northbridge/amd/amdk8/setup_resource_map.c"
  53
  54 #include "southbridge/amd/rs690/rs690_early_setup.c"
  55 #include "southbridge/amd/sb600/sb600_early_setup.c"
  56
  57 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  58 static void memreset(int controllers, const struct mem_controller *ctrl)
  59 {
  60 }
  61
  62 /* called in raminit_f.c */
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 /*called in raminit_f.c */
  68 static inline int spd_read_byte(u32 device, u32 address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #include "northbridge/amd/amdk8/amdk8.h"
  74 #include "northbridge/amd/amdk8/incoherent_ht.c"
  75 #include "northbridge/amd/amdk8/raminit_f.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "lib/generic_sdram.c"
  78 #include "resourcemap.c"
  79
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82
  83 #include "cpu/amd/car/post_cache_as_ram.c"
  84
  85 #include "cpu/amd/model_fxx/init_cpus.c"
  86
  87 #include "cpu/amd/model_fxx/fidvid.c"
  88
  89 #include "northbridge/amd/amdk8/early_ht.c"
  90
  91 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  92 {
  93         device_t dev;
  94         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  95         int needs_reset = 0;
  96         u32 bsp_apicid = 0;
  97         msr_t msr;
  98         struct cpuid_result cpuid1;
  99         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 100
 101         if (!cpu_init_detectedx && boot_cpu()) {
 102                 /* Nothing special needs to be done to find bus 0 */
 103                 /* Allow the HT devices to be found */
 104                 enumerate_ht_chain();
 105
 106                 /* sb600_lpc_port80(); */
 107                 sb600_pci_port80();
 108         }
 109
 110         if (bist == 0) {
 111                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 112         }
 113
 114         enable_rs690_dev8();
 115         sb600_lpc_init();
 116
 117         dev=PNP_DEV(0x2e, W83627DHG_SP1);
 118         w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
 119         uart_init();
 120
 121 #if CONFIG_USBDEBUG
 122         sb600_enable_usbdebug(0);
 123         early_usbdebug_init();
 124 #endif
 125
 126         console_init();
 127
 128         /* Halt if there was a built in self test failure */
 129         report_bist_failure(bist);
 130         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 131
 132         setup_kt690_resource_map();
 133
 134         setup_coherent_ht_domain();
 135
 136 #if CONFIG_LOGICAL_CPUS==1
 137         /* It is said that we should start core1 after all core0 launched */
 138         wait_all_core0_started();
 139         start_other_cores();
 140 #endif
 141         wait_all_aps_started(bsp_apicid);
 142
 143         ht_setup_chains_x(sysinfo);
 144
 145         /* run _early_setup before soft-reset. */
 146         rs690_early_setup();
 147         sb600_early_setup();
 148
 149         /* Check to see if processor is capable of changing FIDVID  */
 150         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 151         cpuid1 = cpuid(0x80000007);
 152         if( (cpuid1.edx & 0x6) == 0x6 ) {
 153
 154                 /* Read FIDVID_STATUS */
 155                 msr=rdmsr(0xc0010042);
 156                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 157
 158                 enable_fid_change();
 159                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 160                 init_fidvid_bsp(bsp_apicid);
 161
 162                 /* show final fid and vid */
 163                 msr=rdmsr(0xc0010042);
 164                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 165
 166         } else {
 167                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 168                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 169         }
 170
 171         needs_reset = optimize_link_coherent_ht();
 172         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 173         rs690_htinit();
 174         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 175
 176         if (needs_reset) {
 177                 print_info("ht reset -\n");
 178                 soft_reset();
 179         }
 180
 181         allow_all_aps_stop(bsp_apicid);
 182
 183         /* It's the time to set ctrl now; */
 184         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 185                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 186         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 187         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 188
 189         rs690_before_pci_init();
 190         sb600_before_pci_init();
 191
 192         post_cache_as_ram();
 193 }
 194