2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
26 #include <cpu/amd/amdk8_sysconf.h>
28 extern u8 bus_rs690[8];
29 extern u8 bus_sb600[2];
31 extern u32 apicid_sb600;
33 extern u32 sbdn_rs690;
34 extern u32 sbdn_sb600;
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
43 mptable_init(mc, LOCAL_APIC_ADDR);
45 smp_write_processors(mc);
49 mptable_write_buses(mc, NULL, &bus_isa);
51 /* I/O APICs: APIC ID Version State Address */
58 dev_find_slot(bus_sb600[0],
59 PCI_DEVFN(sbdn_sb600 + 0x14, 0));
61 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
62 smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
64 /* Initialize interrupt mapping */
66 byte = pci_read_config8(dev, 0x63);
68 byte |= 0; /* 0: INTA, ...., 7: INTH */
69 pci_write_config8(dev, 0x63, byte);
72 dword = pci_read_config32(dev, 0xac);
74 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
75 /* dword |= 1<<22; PIC and APIC co exists */
76 pci_write_config32(dev, 0xac, dword);
79 * 00:12.0: PROG SATA : INT F
87 * 00:14.2: Prog HDA : INT E
94 #define IO_LOCAL_INT(type, intr, apicid, pin) \
95 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
97 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
99 /* PCI interrupts are level triggered, and are
100 * associated with a specific bus/device/function tuple.
102 #if CONFIG_GENERATE_ACPI_TABLES == 0
103 #define PCI_INT(bus, dev, fn, pin) \
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
106 #define PCI_INT(bus, dev, fn, pin)
110 PCI_INT(0x0, 0x13, 0x0, 0x10);
111 PCI_INT(0x0, 0x13, 0x1, 0x11);
112 PCI_INT(0x0, 0x13, 0x2, 0x12);
113 PCI_INT(0x0, 0x13, 0x3, 0x13);
116 PCI_INT(0x0, 0x12, 0x0, 0x16);
118 /* HD Audio: b0:d20:f1:reg63 should be 0. */
119 PCI_INT(0x0, 0x14, 0x0, 0x10);
121 /* on board NIC & Slot PCIE. */
122 PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
123 PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
124 PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
125 PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
126 PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
127 PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
128 PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
129 PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
133 PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
134 PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
135 PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
136 PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
139 PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
140 PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
141 PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
142 PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
145 PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
146 PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
147 PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
148 PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
150 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
151 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
152 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
153 /* There is no extension information... */
155 /* Compute the checksums */
156 return mptable_finalize(mc);
159 unsigned long write_smp_table(unsigned long addr)
162 v = smp_write_floating_table(addr, 0);
163 return (unsigned long)smp_write_config_table(v);