2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
5 ## Copyright (C) 2009 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 uses CONFIG_GENERATE_MP_TABLE
24 uses CONFIG_GENERATE_PIRQ_TABLE
25 uses CONFIG_GENERATE_ACPI_TABLES
26 uses CONFIG_HAVE_ACPI_RESUME
27 uses CONFIG_USE_FALLBACK_IMAGE
28 uses CONFIG_HAVE_FALLBACK_BOOT
29 uses CONFIG_HAVE_HARD_RESET
30 uses CONFIG_IRQ_SLOT_COUNT
31 uses CONFIG_HAVE_OPTION_TABLE
33 uses CONFIG_MAX_PHYSICAL_CPUS
34 uses CONFIG_LOGICAL_CPUS
37 uses CONFIG_FALLBACK_SIZE
39 uses CONFIG_ROM_SECTION_SIZE
40 uses CONFIG_ROM_IMAGE_SIZE
41 uses CONFIG_ROM_SECTION_SIZE
42 uses CONFIG_ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
46 uses CONFIG_XIP_ROM_SIZE
47 uses CONFIG_XIP_ROM_BASE
48 uses CONFIG_STACK_SIZE
50 uses CONFIG_USE_OPTION_TABLE
51 uses CONFIG_LB_CKS_RANGE_START
52 uses CONFIG_LB_CKS_RANGE_END
53 uses CONFIG_LB_CKS_LOC
54 uses CONFIG_MAINBOARD_PART_NUMBER
55 uses CONFIG_MAINBOARD_VENDOR
57 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
58 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
59 uses COREBOOT_EXTRA_VERSION
61 uses CONFIG_TTYS0_BAUD
62 uses CONFIG_TTYS0_BASE
64 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
65 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
66 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
67 uses CONFIG_CONSOLE_SERIAL8250
68 uses CONFIG_HAVE_INIT_TIMER
71 uses CONFIG_CROSS_COMPILE
75 uses CONFIG_CONSOLE_VGA
76 uses CONFIG_PCI_ROM_RUN
77 uses CONFIG_HW_MEM_HOLE_SIZEK
78 uses CONFIG_HT_CHAIN_UNITID_BASE
79 uses CONFIG_HT_CHAIN_END_UNITID_BASE
80 uses CONFIG_SB_HT_CHAIN_ON_BUS0
82 uses CONFIG_USE_DCACHE_RAM
83 uses CONFIG_DCACHE_RAM_BASE
84 uses CONFIG_DCACHE_RAM_SIZE
85 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
88 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
89 uses CONFIG_USE_PRINTK_IN_CAR
93 uses CONFIG_HAVE_MAINBOARD_RESOURCES
100 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
102 default CONFIG_ROM_SIZE=524288
105 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
107 #default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
109 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
112 ## Build code for the fallback boot
114 default CONFIG_HAVE_FALLBACK_BOOT=1
117 ## Build code to reset the motherboard from coreboot
119 default CONFIG_HAVE_HARD_RESET=1
122 ## Build code to export a programmable irq routing table
124 default CONFIG_GENERATE_PIRQ_TABLE=1
125 default CONFIG_IRQ_SLOT_COUNT=11
128 ## Build code to export an x86 MP table
129 ## Useful for specifying IRQ routing values
131 default CONFIG_GENERATE_MP_TABLE=1
133 ## ACPI tables will be included
134 default CONFIG_GENERATE_ACPI_TABLES=1
137 ## Build code to export a CMOS option table
139 default CONFIG_HAVE_OPTION_TABLE=0
142 ## Move the default coreboot cmos range off of AMD RTC registers
144 default CONFIG_LB_CKS_RANGE_START=49
145 default CONFIG_LB_CKS_RANGE_END=122
146 default CONFIG_LB_CKS_LOC=123
149 ## Build code for SMP support
150 ## Only worry about 2 micro processors
153 default CONFIG_MAX_CPUS=2
155 default CONFIG_MAX_PHYSICAL_CPUS=1
156 default CONFIG_LOGICAL_CPUS=1
159 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
162 default CONFIG_CONSOLE_VGA=1
163 default CONFIG_PCI_ROM_RUN=1
165 # BTDC: Only one HT device on Herring.
167 #default CONFIG_HT_CHAIN_UNITID_BASE=0x6
168 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
172 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
174 #make the SB HT chain on bus 0
175 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
178 ## enable CACHE_AS_RAM specifics
180 default CONFIG_USE_DCACHE_RAM=1
181 default CONFIG_DCACHE_RAM_BASE=0xc8000
182 default CONFIG_DCACHE_RAM_SIZE=0x8000
183 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
184 default CONFIG_USE_INIT=0
187 ## Build code to setup a generic IOAPIC
189 default CONFIG_IOAPIC=1
192 ## Clean up the motherboard id strings
194 default CONFIG_MAINBOARD_PART_NUMBER="KT690"
195 default CONFIG_MAINBOARD_VENDOR="KONTRON"
196 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1488
197 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6900
201 ### coreboot layout values
204 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
205 default CONFIG_ROM_IMAGE_SIZE = 65536
208 ## Use a small 32K stack
210 default CONFIG_STACK_SIZE=0x8000
213 ## Use a small 32K heap
215 default CONFIG_HEAP_SIZE=0x8000
218 ## Only use the option table in a normal image
220 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
221 default CONFIG_USE_OPTION_TABLE = 0
224 ## coreboot C code runs at this location in RAM
226 default CONFIG_RAMBASE=0x00100000
229 ## Load the payload from the ROM
231 default CONFIG_ROM_PAYLOAD = 1
234 ### Defaults of options that you may want to override in the target config file
238 ## The default compiler
240 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
244 ## Disable the gdb stub by default
246 default CONFIG_GDB_STUB=0
249 default CONFIG_USE_PRINTK_IN_CAR=1
252 ## The Serial Console
255 # To Enable the Serial Console
256 default CONFIG_CONSOLE_SERIAL8250=1
258 ## Select the serial console baud rate
259 default CONFIG_TTYS0_BAUD=115200
260 #default CONFIG_TTYS0_BAUD=57600
261 #default CONFIG_TTYS0_BAUD=38400
262 #default CONFIG_TTYS0_BAUD=19200
263 #default CONFIG_TTYS0_BAUD=9600
264 #default CONFIG_TTYS0_BAUD=4800
265 #default CONFIG_TTYS0_BAUD=2400
266 #default CONFIG_TTYS0_BAUD=1200
268 # Select the serial console base port
269 default CONFIG_TTYS0_BASE=0x3f8
271 # Select the serial protocol
272 # This defaults to 8 data bits, 1 stop bit, and no parity
273 default CONFIG_TTYS0_LCS=0x3
276 ### Select the coreboot loglevel
278 ## EMERG 1 system is unusable
279 ## ALERT 2 action must be taken immediately
280 ## CRIT 3 critical conditions
281 ## ERR 4 error conditions
282 ## WARNING 5 warning conditions
283 ## NOTICE 6 normal but significant condition
284 ## INFO 7 informational
285 ## CONFIG_DEBUG 8 debug-level messages
286 ## SPEW 9 Way too many details
288 ## Request this level of debugging output
289 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
290 ## At a maximum only compile in this level of debugging
291 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
294 ## Select power on after power fail setting
295 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
297 default CONFIG_VIDEO_MB=1
298 default CONFIG_GFXUMA=1
299 default CONFIG_HAVE_MAINBOARD_RESOURCES=1