src/mainboard/kontron/986lcd-m/auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 // __ROMCC__ means: use "unsigned" for device, not a struct.
  23 #define __ROMCC__
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <arch/io.h>
  28 #include <arch/romcc_io.h>
  29 #include <device/pci_def.h>
  30 #include <device/pnp_def.h>
  31 #include <cpu/x86/lapic.h>
  32
  33 #include "superio/winbond/w83627thg/w83627thg.h"
  34
  35 #include "option_table.h"
  36 #include "pc80/mc146818rtc_early.c"
  37
  38 #include "pc80/serial.c"
  39 #include "arch/i386/lib/console.c"
  40 #include <cpu/x86/bist.h>
  41
  42 #include "ram/ramtest.c"
  43 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
  44 #include "reset.c"
  45 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
  46
  47 #include "northbridge/intel/i945/udelay.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
  50
  51 #include "northbridge/intel/i945/ich7.h"
  52 static void setup_ich7_gpios(void)
  53 {
  54         /* TODO: This is highly board specific and should be moved */
  55         printk_debug(" GPIOS...");
  56         /* General Registers */
  57         outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  58         outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  59         outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  60         /* Output Control Registers */
  61         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  62         /* Input Control Registers */
  63         outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  64         outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  65         outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  66         outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  67 }
  68
  69 #include "northbridge/intel/i945/early_init.c"
  70
  71 static inline int spd_read_byte(unsigned device, unsigned address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 /* Usually system firmware turns off system memory clock signals to
  77  * unused SO-DIMM slots to reduce EMI and power consumption.
  78  * However, the Kontron 986LCD-M does not like unused clock signals to
  79  * be disabled. If other similar mainboard occur, it would make sense
  80  * to make this an entry in the sysinfo structure, and pre-initialize that
  81  * structure in the mainboard's auto.c main() function. For now a
  82  * #define will do.
  83  */
  84 #define OVERRIDE_CLOCK_DISABLE 1
  85
  86 #define CHANNEL_XOR_RANDOMIZATION 1
  87 #include "northbridge/intel/i945/raminit.h"
  88 #include "northbridge/intel/i945/raminit.c"
  89 #include "northbridge/intel/i945/reset_test.c"
  90 #include "northbridge/intel/i945/errata.c"
  91 #include "debug.c"
  92
  93 static void ich7_enable_lpc(void)
  94 {
  95         // Enable Serial IRQ
  96         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  97         // Set COM1/COM2 decode range
  98         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
  99         // Enable COM1/COM2/KBD/SuperIO1+2
 100         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
 101         // Enable HWM at 0xa00
 102         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
 103         // COM3 decode
 104         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
 105         // COM4 decode
 106         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
 107         // io 0x300 decode
 108         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
 109 }
 110
 111
 112 /* This box has two superios, so enabling serial becomes slightly excessive.
 113  * We disable a lot of stuff to make sure that there are no conflicts between
 114  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
 115  * but safe anyways" method.
 116  */
 117 static void early_superio_config_w83627thg(void)
 118 {
 119         device_t dev;
 120
 121         dev=PNP_DEV(0x2e, W83627THG_SP1);
 122         pnp_enter_ext_func_mode(dev);
 123
 124         pnp_set_logical_device(dev);
 125         pnp_set_enable(dev, 0);
 126         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
 127         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
 128         pnp_set_enable(dev, 1);
 129
 130         dev=PNP_DEV(0x2e, W83627THG_SP2);
 131         pnp_set_logical_device(dev);
 132         pnp_set_enable(dev, 0);
 133         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 134         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
 135         // pnp_write_config(dev, 0xf1, 4); // IRMODE0
 136         pnp_set_enable(dev, 1);
 137
 138         dev=PNP_DEV(0x2e, W83627THG_KBC);
 139         pnp_set_logical_device(dev);
 140         pnp_set_enable(dev, 0);
 141         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 142         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
 143         // pnp_write_config(dev, 0xf0, 0x82);
 144         pnp_set_enable(dev, 1);
 145
 146         dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
 147         pnp_set_logical_device(dev);
 148         pnp_set_enable(dev, 0);
 149         pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
 150         pnp_set_enable(dev, 1);
 151
 152         dev=PNP_DEV(0x2e, W83627THG_GPIO2);
 153         pnp_set_logical_device(dev);
 154         pnp_set_enable(dev, 1); // Just enable it
 155
 156         dev=PNP_DEV(0x2e, W83627THG_GPIO3);
 157         pnp_set_logical_device(dev);
 158         pnp_set_enable(dev, 0);
 159         pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 160         pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 161         pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 162
 163         dev=PNP_DEV(0x2e, W83627THG_FDC);
 164         pnp_set_logical_device(dev);
 165         pnp_set_enable(dev, 0);
 166
 167         dev=PNP_DEV(0x2e, W83627THG_PP);
 168         pnp_set_logical_device(dev);
 169         pnp_set_enable(dev, 0);
 170
 171         /* Enable HWM */
 172         dev=PNP_DEV(0x2e, W83627THG_HWM);
 173         pnp_set_logical_device(dev);
 174         pnp_set_enable(dev, 0);
 175         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 176         pnp_set_enable(dev, 1);
 177
 178         pnp_exit_ext_func_mode(dev);
 179
 180         dev=PNP_DEV(0x4e, W83627THG_SP1);
 181         pnp_enter_ext_func_mode(dev);
 182
 183         pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
 184         pnp_set_enable(dev, 0);
 185         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
 186         pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
 187         pnp_set_enable(dev, 1);
 188
 189         dev=PNP_DEV(0x4e, W83627THG_SP2);
 190         pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
 191         pnp_set_enable(dev, 0);
 192         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
 193         pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
 194         pnp_set_enable(dev, 1);
 195
 196         dev=PNP_DEV(0x4e, W83627THG_FDC);
 197         pnp_set_logical_device(dev);
 198         pnp_set_enable(dev, 0);
 199
 200         dev=PNP_DEV(0x4e, W83627THG_PP);
 201         pnp_set_logical_device(dev);
 202         pnp_set_enable(dev, 0);
 203
 204         dev=PNP_DEV(0x4e, W83627THG_KBC);
 205         pnp_set_logical_device(dev);
 206         pnp_set_enable(dev, 0);
 207         pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
 208         pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
 209
 210         pnp_exit_ext_func_mode(dev);
 211 }
 212
 213 static void rcba_config(void)
 214 {
 215         /* Set up virtual channel 0 */
 216         //RCBA32(0x0014) = 0x80000001;
 217         //RCBA32(0x001c) = 0x03128010;
 218
 219         /* Device 1f interrupt pin register */
 220         RCBA32(0x3100) = 0x00042210;
 221         /* Device 1d interrupt pin register */
 222         RCBA32(0x310c) = 0x00214321;
 223
 224         /* dev irq route register */
 225         RCBA16(0x3140) = 0x0132;
 226         RCBA16(0x3142) = 0x3241;
 227         RCBA16(0x3144) = 0x0237;
 228         RCBA16(0x3146) = 0x3210;
 229         RCBA16(0x3148) = 0x3210;
 230
 231         /* Enable IOAPIC */
 232         RCBA8(0x31ff) = 0x03;
 233
 234         /* Enable upper 128bytes of CMOS */
 235         RCBA32(0x3400) = (1 << 2);
 236
 237         /* Disable unused devices */
 238         RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
 239         RCBA32(0x3418) |= (1 << 0); // Required.
 240
 241         /* Enable PCIe Root Port Clock Gate */
 242         // RCBA32(0x341c) = 0x00000001;
 243 }
 244
 245 static void early_ich7_init(void)
 246 {
 247         uint8_t reg8;
 248         uint32_t reg32;
 249
 250         // program secondary mlt XXX byte?
 251         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 252
 253         // reset rtc power status
 254         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 255         reg8 &= ~(1 << 2);
 256         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 257
 258         // usb transient disconnect
 259         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 260         reg8 |= (3 << 0);
 261         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 262
 263         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 264         reg32 |= (1 << 29) | (1 << 17);
 265         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 266
 267         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 268         reg32 |= (1 << 31) | (1 << 27);
 269         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 270
 271         RCBA32(0x0088) = 0x0011d000;
 272         RCBA16(0x01fc) = 0x060f;
 273         RCBA32(0x01f4) = 0x86000040;
 274         RCBA32(0x0214) = 0x10030549;
 275         RCBA32(0x0218) = 0x00020504;
 276         RCBA8(0x0220) = 0xc5;
 277         reg32 = RCBA32(0x3410);
 278         reg32 |= (1 << 6);
 279         RCBA32(0x3410) = reg32;
 280         reg32 = RCBA32(0x3430);
 281         reg32 &= ~(3 << 0);
 282         reg32 |= (1 << 0);
 283         RCBA32(0x3430) = reg32;
 284         RCBA32(0x3418) |= (1 << 0);
 285         RCBA16(0x0200) = 0x2008;
 286         RCBA8(0x2027) = 0x0d;
 287         RCBA16(0x3e08) |= (1 << 7);
 288         RCBA16(0x3e48) |= (1 << 7);
 289         RCBA32(0x3e0e) |= (1 << 7);
 290         RCBA32(0x3e4e) |= (1 << 7);
 291
 292         // next step only on ich7m b0 and later:
 293         reg32 = RCBA32(0x2034);
 294         reg32 &= ~(0x0f << 16);
 295         reg32 |= (5 << 16);
 296         RCBA32(0x2034) = reg32;
 297 }
 298
 299 #if USE_FALLBACK_IMAGE == 1
 300 #include "southbridge/intel/i82801gx/cmos_failover.c"
 301 #endif
 302
 303 void real_main(unsigned long bist)
 304 {
 305         int boot_mode = 0;
 306
 307         if (bist == 0) {
 308                 enable_lapic();
 309         }
 310
 311         ich7_enable_lpc();
 312         early_superio_config_w83627thg();
 313
 314         /* Set up the console */
 315         uart_init();
 316         console_init();
 317
 318         /* Halt if there was a built in self test failure */
 319         report_bist_failure(bist);
 320
 321         if (MCHBAR16(SSKPD) == 0xCAFE) {
 322                 printk_debug("soft reset detected.\n");
 323                 boot_mode = 1;
 324         }
 325
 326         /* Perform some early chipset initialization required
 327          * before RAM initialization can work
 328          */
 329         i945_early_initialization();
 330
 331         /* Enable SPD ROMs and DDR-II DRAM */
 332         enable_smbus();
 333
 334 #if DEFAULT_CONSOLE_LOGLEVEL > 8
 335         dump_spd_registers();
 336 #endif
 337
 338         sdram_initialize(boot_mode);
 339
 340         /* Perform some initialization that must run before stage2 */
 341         early_ich7_init();
 342
 343         /* This should probably go away. Until now it is required
 344          * and mainboard specific
 345          */
 346         rcba_config();
 347
 348         /* Chipset Errata! */
 349         fixup_i945_errata();
 350
 351         /* Initialize the internal PCIe links before we go into stage2 */
 352         i945_late_initialization();
 353
 354 #if DEFAULT_CONSOLE_LOGLEVEL > 8
 355 #if defined(DEBUG_RAM_SETUP)
 356         sdram_dump_mchbar_registers();
 357 #endif
 358
 359         {
 360                 /* This will not work if TSEG is in place! */
 361                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 362
 363                 printk_debug("TOM: 0x%08x\n", tom);
 364                 ram_check(0x00000000, 0x000a0000);
 365                 ram_check(0x00100000, tom);
 366         }
 367 #endif
 368         MCHBAR16(SSKPD) = 0xCAFE;
 369 }
 370
 371 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"