src/mainboard/kontron/986lcd-m/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007-2008 coresystems GmbH
   5 ##
   6 ## This program is free software; you can redistribute it and/or
   7 ## modify it under the terms of the GNU General Public License as
   8 ## published by the Free Software Foundation; version 2 of
   9 ## the License.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16 ## You should have received a copy of the GNU General Public License
  17 ## along with this program; if not, write to the Free Software
  18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19 ## MA 02110-1301 USA
  20 ##
  21
  22 ##
  23 ## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
  24 ##
  25
  26 ##
  27 ## Only use the option table in a normal image
  28 ##
  29 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
  30
  31 include /config/nofailovercalculation.lb
  32
  33 ##
  34 ## Set all of the defaults for an x86 architecture
  35 ##
  36
  37 arch i386 end
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44 driver rtl8168.o
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47 if HAVE_SMI_HANDLER smmobject mainboard_smi.o end
  48
  49 if HAVE_ACPI_TABLES
  50         object fadt.o
  51         object acpi_tables.o
  52         makerule dsdt.c
  53                 depends "$(MAINBOARD)/dsdt.asl"
  54                 action  "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl"
  55                 action  "mv $(PWD)/dsdt.hex dsdt.c"
  56         end
  57         object ./dsdt.o
  58 end
  59
  60 object reset.o
  61
  62 if CONFIG_USE_INIT
  63
  64 makerule ./auto.o
  65         depends "$(MAINBOARD)/auto.c option_table.h"
  66         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/auto.c -o $@"
  67 end
  68
  69 else
  70
  71 makerule ./auto.inc
  72         depends "$(MAINBOARD)/auto.c option_table.h"
  73         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@"
  74         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  75         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  76 end
  77
  78 end
  79
  80 ##
  81 ## Build our 16 bit and 32 bit coreboot entry code
  82 ##
  83 mainboardinit cpu/x86/16bit/entry16.inc
  84 mainboardinit cpu/x86/32bit/entry32.inc
  85 ldscript /cpu/x86/16bit/entry16.lds
  86 if CONFIG_USE_INIT
  87         ldscript /cpu/x86/32bit/entry32.lds
  88         ldscript /cpu/x86/car/cache_as_ram.lds
  89 end
  90
  91 ##
  92 ## Build our reset vector (This is where coreboot is entered)
  93 ##
  94 if USE_FALLBACK_IMAGE
  95         mainboardinit cpu/x86/16bit/reset16.inc
  96         ldscript /cpu/x86/16bit/reset16.lds
  97 else
  98         mainboardinit cpu/x86/32bit/reset32.inc
  99         ldscript /cpu/x86/32bit/reset32.lds
 100 end
 101
 102
 103 ##
 104 ## Include an id string (For safe flashing)
 105 ##
 106 mainboardinit arch/i386/lib/id.inc
 107 ldscript /arch/i386/lib/id.lds
 108
 109 ##
 110 ## Setup Cache-As-Ram
 111 ##
 112 mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
 113
 114 ###
 115 ### This is the early phase of coreboot startup
 116 ### Things are delicate and we test to see if we should
 117 ### failover to another image.
 118 ###
 119 if USE_FALLBACK_IMAGE
 120         ldscript /arch/i386/lib/failover.lds
 121 end
 122
 123 ###
 124 ### O.k. We aren't just an intermediary anymore!
 125 ###
 126
 127 if CONFIG_USE_INIT
 128 initobject auto.o
 129 else
 130 mainboardinit ./auto.inc
 131 end
 132
 133 ##
 134 ## Include the secondary Configuration files
 135 ##
 136 dir /pc80
 137 config chip.h
 138
 139 chip northbridge/intel/i945
 140
 141         device apic_cluster 0 on
 142                 chip cpu/intel/socket_mFCPGA478
 143                         device apic 0 on end
 144                 end
 145         end
 146
 147         device pci_domain 0 on
 148                 device pci 00.0 on end # host bridge
 149                 device pci 01.0 off end # i945 PCIe root port
 150                 chip drivers/pci/onboard
 151                         device pci 02.0 on end # vga controller
 152                         # register "rom_address" = "0xfffc0000" # 256 KB image
 153                         # register "rom_address" = "0xfff80000" # 512 KB image
 154                         register "rom_address" = "0xfff00000" # 1 MB image
 155                 end
 156                 device pci 02.1 on end # display controller
 157
 158                 chip southbridge/intel/i82801gx
 159                         register "pirqa_routing" = "0x05"
 160                         register "pirqb_routing" = "0x07"
 161                         register "pirqc_routing" = "0x05"
 162                         register "pirqd_routing" = "0x07"
 163                         register "pirqe_routing" = "0x80"
 164                         register "pirqf_routing" = "0x80"
 165                         register "pirqg_routing" = "0x80"
 166                         register "pirqh_routing" = "0x06"
 167
 168                         # GPI routing
 169                         #  0 No effect (default)
 170                         #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
 171                         #  2 SCI (if corresponding GPIO_EN bit is also set)
 172                         register "gpi13_routing" = "1"
 173
 174                         register "ide_legacy_combined" = "0x1"
 175                         register "ide_enable_primary" = "0x1"
 176                         register "ide_enable_secondary" = "0x0"
 177                         register "sata_ahci" = "0x0"
 178
 179                         device pci 1b.0 on end # High Definition Audio
 180                         device pci 1c.0 on end # PCIe
 181                         device pci 1c.1 on end # PCIe
 182                         device pci 1c.2 on end # PCIe
 183                         #device pci 1c.3 off end # PCIe port 4
 184                         #device pci 1c.4 off end # PCIe port 5
 185                         #device pci 1c.5 off end # PCIe port 6
 186                         device pci 1d.0 on end # USB UHCI
 187                         device pci 1d.1 on end # USB UHCI
 188                         device pci 1d.2 on end # USB UHCI
 189                         device pci 1d.3 on end # USB UHCI
 190                         device pci 1d.7 on end # USB2 EHCI
 191                         device pci 1e.0 on end # PCI bridge
 192                         #device pci 1e.2 off end # AC'97 Audio
 193                         #device pci 1e.3 off end # AC'97 Modem
 194                         device pci 1f.0 on # LPC bridge
 195                                 chip superio/winbond/w83627thg
 196                                         device pnp 2e.0 off             # Floppy
 197                                         end
 198                                         device pnp 2e.1 off             # Parport
 199                                         end
 200                                         device pnp 2e.2 on
 201                                                  io 0x60 = 0x3f8
 202                                                 irq 0x70 = 4
 203                                         end
 204                                         device pnp 2e.3 on
 205                                                  io 0x60 = 0x2f8
 206                                                 irq 0x70 = 3
 207                                                 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
 208                                         end
 209                                         device pnp 2e.5 on              # Keyboard+Mouse
 210                                                  io 0x60 = 0x60
 211                                                  io 0x62 = 0x64
 212                                                 irq 0x70 = 1
 213                                                 irq 0x72 = 12
 214                                                 irq 0xf0 = 0x82         # HW accel A20.
 215                                         end
 216                                         device pnp 2e.7 on              # GPIO1, GAME, MIDI
 217                                                  io 0x62 = 0x330
 218                                                 irq 0x70 = 9
 219                                         end
 220                                         device pnp 2e.8 on              # GPIO2
 221                                                 # all default
 222                                         end
 223                                         device pnp 2e.9 on              # GPIO3/4
 224                                                 irq 0x30 = 0x03         # does this work?
 225                                                 irq 0xf0 = 0xfb         # set inputs/outputs
 226                                                 irq 0xf1 = 0x66
 227                                         end
 228                                         device pnp 2e.a off             # ACPI
 229                                         end
 230                                         device pnp 2e.b on              # HWM
 231                                                  io 0x60 = 0xa00
 232                                                 irq 0x70 = 0
 233                                         end
 234
 235                                 end
 236                                 chip superio/winbond/w83627thg
 237                                         device pnp 4e.0 off             # Floppy
 238                                         end
 239                                         device pnp 4e.1 off             # Parport
 240                                         end
 241                                         device pnp 4e.2 on              # COM3
 242                                                  io 0x60 = 0x3e8
 243                                                 irq 0x70 = 11
 244                                         end
 245                                         device pnp 4e.3 on              # COM4
 246                                                  io 0x60 = 0x2e8
 247                                                 irq 0x70 = 10
 248                                         end
 249                                         device pnp 4e.5 off             # Keyboard
 250                                         end
 251                                         device pnp 4e.7 off             # GPIO1, GAME, MIDI
 252                                         end
 253                                         device pnp 4e.8 off             # GPIO2
 254                                         end
 255                                         device pnp 4e.9 off             # GPIO3/4
 256                                         end
 257                                         device pnp 4e.a off             # ACPI
 258                                         end
 259                                         device pnp 4e.b off             # HWM
 260                                         end
 261                                 end
 262
 263                         end
 264                         #device pci 1f.1 off end # IDE
 265                         device pci 1f.2 on end  # SATA
 266                         device pci 1f.3 on end  # SMBus
 267                         #device pci 1f.4 off end # Realtek ID Codec
 268                 end
 269         end
 270 end