2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 ## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
27 ## Only use the option table in a normal image
29 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
32 ## Compute the location and size of where this firmware image
33 ## (coreboot plus bootloader) will live in the boot rom chip.
36 default ROM_SECTION_SIZE = FALLBACK_SIZE
37 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
39 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
40 default ROM_SECTION_OFFSET = 0
44 ## Compute the start location and size size of
45 ## The coreboot bootloader.
47 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
48 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
51 ## Compute where this copy of coreboot will start in the boot rom
53 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
56 ## Compute a range of ROM that can cached to speed up coreboot,
59 ## XIP_ROM_SIZE must be a power of 2.
60 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
62 default XIP_ROM_SIZE=(64*1024)
63 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
66 ## Set all of the defaults for an x86 architecture
72 ## Build the objects we have code for in this directory.
77 if HAVE_MP_TABLE object mptable.o end
78 if HAVE_PIRQ_TABLE object irq_tables.o end
84 depends "$(MAINBOARD)/dsdt.dsl"
85 action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
86 action "mv $(PWD)/dsdt.hex dsdt.c"
96 depends "$(MAINBOARD)/auto.c option_table.h"
97 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
103 depends "$(MAINBOARD)/auto.c option_table.h"
104 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@"
105 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
106 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
112 ## Build our 16 bit and 32 bit coreboot entry code
114 mainboardinit cpu/x86/16bit/entry16.inc
115 mainboardinit cpu/x86/32bit/entry32.inc
116 ldscript /cpu/x86/16bit/entry16.lds
118 ldscript /cpu/x86/32bit/entry32.lds
119 ldscript /cpu/x86/car/cache_as_ram.lds
123 ## Build our reset vector (This is where coreboot is entered)
125 if USE_FALLBACK_IMAGE
126 mainboardinit cpu/x86/16bit/reset16.inc
127 ldscript /cpu/x86/16bit/reset16.lds
129 mainboardinit cpu/x86/32bit/reset32.inc
130 ldscript /cpu/x86/32bit/reset32.lds
135 ## Include an id string (For safe flashing)
137 mainboardinit arch/i386/lib/id.inc
138 ldscript /arch/i386/lib/id.lds
141 ## Setup Cache-As-Ram
143 mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
146 ### This is the early phase of coreboot startup
147 ### Things are delicate and we test to see if we should
148 ### failover to another image.
150 if USE_FALLBACK_IMAGE
151 ldscript /arch/i386/lib/failover.lds
155 ### O.k. We aren't just an intermediary anymore!
161 mainboardinit ./auto.inc
165 ## Include the secondary Configuration files
170 chip northbridge/intel/i945
172 device apic_cluster 0 on
173 chip cpu/intel/socket_mFCPGA478
178 device pci_domain 0 on
179 device pci 00.0 on end # host bridge
180 device pci 01.0 off end # i945 PCIe root port
181 chip drivers/pci/onboard
182 device pci 02.0 on end # vga controller
183 # register "rom_address" = "0xfffc0000" # 256 KB image
184 # register "rom_address" = "0xfff80000" # 512 KB image
185 register "rom_address" = "0xfff00000" # 1 MB image
187 device pci 02.1 on end # display controller
189 chip southbridge/intel/i82801gx
190 register "pirqa_routing" = "0x05"
191 register "pirqb_routing" = "0x07"
192 register "pirqc_routing" = "0x06"
193 register "pirqd_routing" = "0x07"
194 register "pirqe_routing" = "0x80"
195 register "pirqf_routing" = "0x80"
196 register "pirqg_routing" = "0x80"
197 register "pirqh_routing" = "0x05"
199 register "ide_legacy_combined" = "0x1"
200 register "ide_enable_primary" = "0x1"
201 register "ide_enable_secondary" = "0x0"
202 register "sata_ahci" = "0x0"
204 device pci 1b.0 on end # High Definition Audio
205 device pci 1c.0 on end # PCIe
206 device pci 1c.1 on end # PCIe
207 device pci 1c.2 on end # PCIe
208 #device pci 1c.3 off end # PCIe port 4
209 #device pci 1c.4 off end # PCIe port 5
210 #device pci 1c.5 off end # PCIe port 6
211 device pci 1d.0 on end # USB UHCI
212 device pci 1d.1 on end # USB UHCI
213 device pci 1d.2 on end # USB UHCI
214 device pci 1d.3 on end # USB UHCI
215 device pci 1d.7 on end # USB2 EHCI
216 device pci 1e.0 on end # PCI bridge
217 #device pci 1e.2 off end # AC'97 Audio
218 #device pci 1e.3 off end # AC'97 Modem
219 device pci 1f.0 on # LPC bridge
220 chip superio/winbond/w83627thg
221 device pnp 2e.0 off # Floppy
223 device pnp 2e.1 off # Parport
232 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
234 device pnp 2e.5 on # Keyboard+Mouse
239 irq 0xf0 = 0x82 # HW accel A20.
241 device pnp 2e.7 on # GPIO1, GAME, MIDI
245 device pnp 2e.8 on # GPIO2
248 device pnp 2e.9 on # GPIO3/4
249 irq 0x30 = 0x03 # does this work?
250 irq 0xf0 = 0xfb # set inputs/outputs
253 device pnp 2e.a off # ACPI
255 device pnp 2e.b on # HWM
261 chip superio/winbond/w83627thg
262 device pnp 4e.0 off # Floppy
264 device pnp 4e.1 off # Parport
266 device pnp 4e.2 on # COM3
270 device pnp 4e.3 on # COM4
274 device pnp 4e.5 off # Keyboard
276 device pnp 4e.7 off # GPIO1, GAME, MIDI
278 device pnp 4e.8 off # GPIO2
280 device pnp 4e.9 off # GPIO3/4
282 device pnp 4e.a off # ACPI
284 device pnp 4e.b off # HWM
289 #device pci 1f.1 off end # IDE
290 device pci 1f.2 on end # SATA
291 device pci 1f.3 on end # SMBus
292 #device pci 1f.4 off end # Realtek ID Codec