2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 ## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
27 ## Only use the option table in a normal image
29 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
32 ## Image size calculation
35 include /config/nofailovercalculation.lb
38 ## Set all of the defaults for an x86 architecture
44 ## Build the objects we have code for in this directory.
49 if CONFIG_GENERATE_MP_TABLE object mptable.o end
50 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
51 if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
53 if CONFIG_GENERATE_ACPI_TABLES
57 depends "$(CONFIG_MAINBOARD)/dsdt.asl"
58 action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
59 action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
60 action "mv $(CURDIR)/dsdt.hex dsdt.c"
68 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
69 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
75 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
76 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
77 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
78 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
84 ## Build our 16 bit and 32 bit coreboot entry code
86 mainboardinit cpu/x86/16bit/entry16.inc
87 mainboardinit cpu/x86/32bit/entry32.inc
88 ldscript /cpu/x86/16bit/entry16.lds
90 ldscript /cpu/x86/32bit/entry32.lds
91 ldscript /cpu/x86/car/cache_as_ram.lds
95 ## Build our reset vector (This is where coreboot is entered)
97 if CONFIG_USE_FALLBACK_IMAGE
98 mainboardinit cpu/x86/16bit/reset16.inc
99 ldscript /cpu/x86/16bit/reset16.lds
101 mainboardinit cpu/x86/32bit/reset32.inc
102 ldscript /cpu/x86/32bit/reset32.lds
107 ## Include an id string (For safe flashing)
109 mainboardinit arch/i386/lib/id.inc
110 ldscript /arch/i386/lib/id.lds
113 ## Setup Cache-As-Ram
115 mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
118 ### This is the early phase of coreboot startup
119 ### Things are delicate and we test to see if we should
120 ### failover to another image.
122 if CONFIG_USE_FALLBACK_IMAGE
123 ldscript /arch/i386/lib/failover.lds
127 ### O.k. We aren't just an intermediary anymore!
133 mainboardinit ./auto.inc
137 ## Include the secondary Configuration files
142 chip northbridge/intel/i945
144 device apic_cluster 0 on
145 chip cpu/intel/socket_mFCPGA478
150 device pci_domain 0 on
151 device pci 00.0 on end # host bridge
152 # autodetect 0:1.0 because it might or might not be there.
153 # device pci 01.0 off end # i945 PCIe root port
154 device pci 02.0 on end # vga controller
155 device pci 02.1 on end # display controller
157 chip southbridge/intel/i82801gx
158 register "pirqa_routing" = "0x05"
159 register "pirqb_routing" = "0x07"
160 register "pirqc_routing" = "0x05"
161 register "pirqd_routing" = "0x07"
162 register "pirqe_routing" = "0x80"
163 register "pirqf_routing" = "0x80"
164 register "pirqg_routing" = "0x80"
165 register "pirqh_routing" = "0x06"
168 # 0 No effect (default)
169 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
170 # 2 SCI (if corresponding GPIO_EN bit is also set)
171 register "gpi13_routing" = "1"
172 register "gpe0_en" = "0x00000400"
174 register "ide_legacy_combined" = "0x1"
175 register "ide_enable_primary" = "0x1"
176 register "ide_enable_secondary" = "0x1"
177 register "sata_ahci" = "0x0"
179 device pci 1b.0 on end # High Definition Audio
180 device pci 1c.0 on end # PCIe
181 device pci 1c.1 on end # PCIe
182 device pci 1c.2 on end # PCIe
183 #device pci 1c.3 off end # PCIe port 4
184 #device pci 1c.4 off end # PCIe port 5
185 #device pci 1c.5 off end # PCIe port 6
186 device pci 1d.0 on end # USB UHCI
187 device pci 1d.1 on end # USB UHCI
188 device pci 1d.2 on end # USB UHCI
189 device pci 1d.3 on end # USB UHCI
190 device pci 1d.7 on end # USB2 EHCI
191 device pci 1e.0 on end # PCI bridge
192 #device pci 1e.2 off end # AC'97 Audio
193 #device pci 1e.3 off end # AC'97 Modem
194 device pci 1f.0 on # LPC bridge
195 chip superio/winbond/w83627thg
196 device pnp 2e.0 off # Floppy
198 device pnp 2e.1 off # Parport
207 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
209 device pnp 2e.5 on # Keyboard+Mouse
214 irq 0xf0 = 0x82 # HW accel A20.
216 device pnp 2e.7 on # GPIO1, GAME, MIDI
220 device pnp 2e.8 on # GPIO2
223 device pnp 2e.9 on # GPIO3/4
224 irq 0x30 = 0x03 # does this work?
225 irq 0xf0 = 0xfb # set inputs/outputs
228 device pnp 2e.a off # ACPI
230 device pnp 2e.b on # HWM
236 chip superio/winbond/w83627thg
237 device pnp 4e.0 off # Floppy
239 device pnp 4e.1 off # Parport
241 device pnp 4e.2 on # COM3
245 device pnp 4e.3 on # COM4
249 device pnp 4e.5 off # Keyboard
251 device pnp 4e.7 off # GPIO1, GAME, MIDI
253 device pnp 4e.8 off # GPIO2
255 device pnp 4e.9 off # GPIO3/4
257 device pnp 4e.a off # ACPI
259 device pnp 4e.b off # HWM
264 #device pci 1f.1 off end # IDE
265 device pci 1f.2 on end # SATA
266 device pci 1f.3 on end # SMBus
267 #device pci 1f.4 off end # Realtek ID Codec