2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
5 * Copyright (C) 2010 Advanced Micro Devices, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/pci.h>
29 #include <cpu/amd/amdfam10_sysconf.h>
32 extern u8 bus_rs780[11];
33 extern u8 bus_sb700[2];
35 extern u32 apicid_sb700;
37 extern u32 bus_type[256];
38 extern u32 sbdn_rs780;
39 extern u32 sbdn_sb700;
43 static void *smp_write_config_table(void *v)
45 static const char sig[4] = "PCMP";
46 static const char oem[8] = "COREBOOT";
47 static const char productid[12] = "PA78VM5 ";
48 struct mp_config_table *mc;
51 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
52 memset(mc, 0, sizeof(*mc));
54 memcpy(mc->mpc_signature, sig, sizeof(sig));
55 mc->mpc_length = sizeof(*mc); /* initially just the header */
57 mc->mpc_checksum = 0; /* not yet computed */
58 memcpy(mc->mpc_oem, oem, sizeof(oem));
59 memcpy(mc->mpc_productid, productid, sizeof(productid));
62 mc->mpc_entry_count = 0; /* No entries yet... */
63 mc->mpc_lapic = LAPIC_ADDR;
68 smp_write_processors(mc);
72 /* Bus: Bus ID Type */
73 /* define bus and isa numbers */
74 for (j = 0; j < bus_isa; j++) {
75 smp_write_bus(mc, j, (char *)"PCI ");
77 smp_write_bus(mc, bus_isa, (char *)"ISA ");
79 /* I/O APICs: APIC ID Version State Address */
86 dev_find_slot(bus_sb700[0],
87 PCI_DEVFN(sbdn_sb700 + 0x14, 0));
89 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
90 smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
92 /* Initialize interrupt mapping */
94 byte = pci_read_config8(dev, 0x63);
96 byte |= 0; /* 0: INTA, ...., 7: INTH */
97 pci_write_config8(dev, 0x63, byte);
100 dword = pci_read_config32(dev, 0xac);
102 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
103 /* dword |= 1<<22; PIC and APIC co exists */
104 pci_write_config32(dev, 0xac, dword);
107 * 00:12.0: PROG SATA : INT F
108 * 00:13.0: INTA USB_0
109 * 00:13.1: INTB USB_1
110 * 00:13.2: INTC USB_2
111 * 00:13.3: INTD USB_3
112 * 00:13.4: INTC USB_4
115 * 00:14.2: Prog HDA : INT E
122 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
123 #define IO_LOCAL_INT(type, intr, apicid, pin) \
124 smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
126 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
128 /* PCI interrupts are level triggered, and are
129 * associated with a specific bus/device/function tuple.
131 #if CONFIG_GENERATE_ACPI_TABLES == 0
132 #define PCI_INT(bus, dev, fn, pin) \
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
135 #define PCI_INT(bus, dev, fn, pin)
139 PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
140 PCI_INT(0x0, 0x12, 0x1, 0x11);
141 PCI_INT(0x0, 0x13, 0x0, 0x12);
142 PCI_INT(0x0, 0x13, 0x1, 0x13);
143 PCI_INT(0x0, 0x14, 0x0, 0x10);
146 PCI_INT(0x0, 0x11, 0x0, 0x16);
148 /* HD Audio: b0:d20:f1:reg63 should be 0. */
149 /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
151 /* on board NIC & Slot PCIE. */
152 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
153 /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
154 PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
155 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
156 PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
157 /* configuration B doesnt need dev 5,6,7 */
159 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
160 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
161 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
163 PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
164 PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
168 PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
169 PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
170 PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
171 PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
174 PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
175 PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
176 PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
177 PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
180 PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
181 PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
182 PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
183 PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
185 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
186 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
187 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
188 /* There is no extension information... */
190 /* Compute the checksums */
192 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
193 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
194 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
195 mc, smp_next_mpe_entry(mc));
196 return smp_next_mpe_entry(mc);
199 unsigned long write_smp_table(unsigned long addr)
202 v = smp_write_floating_table(addr);
203 return (unsigned long)smp_write_config_table(v);