src/mainboard/iwill/dk8x/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "cpu/x86/bist.h"
  22 #include "lib/delay.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26 #include "northbridge/amd/amdk8/setup_resource_map.c"
  27 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 /*
  32  * GPIO28 of 8111 will control H0_MEMRESET_L
  33  * GPIO29 of 8111 will control H1_MEMRESET_L
  34  */
  35 static void memreset_setup(void)
  36 {
  37         if (is_cpu_pre_c0()) {
  38                 /* Set the memreset low. */
  39                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  40                 /* Ensure the BIOS has control of the memory lines. */
  41                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  42         } else {
  43                 /* Ensure the CPU has control of the memory lines. */
  44                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  45         }
  46 }
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl)
  49 {
  50         if (is_cpu_pre_c0()) {
  51                 udelay(800);
  52                 /* Set memreset high. */
  53                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  54                 udelay(90);
  55         }
  56 }
  57
  58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "northbridge/amd/amdk8/amdk8.h"
  66 #include "northbridge/amd/amdk8/incoherent_ht.c"
  67 #include "northbridge/amd/amdk8/coherent_ht.c"
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "lib/generic_sdram.c"
  70 #include "northbridge/amd/amdk8/resourcemap.c"
  71 #include "cpu/amd/dualcore/dualcore.c"
  72 #include <spd.h>
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75 #include "cpu/amd/model_fxx/fidvid.c"
  76 #include "northbridge/amd/amdk8/early_ht.c"
  77
  78 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  79 {
  80         static const uint16_t spd_addr[] = {
  81                 // first node
  82                 DIMM0, DIMM2, 0, 0,
  83                 DIMM1, DIMM3, 0, 0,
  84
  85                         // second node
  86                 DIMM4, DIMM6, 0, 0,
  87                 DIMM5, DIMM7, 0, 0,
  88         };
  89
  90         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
  91                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  92         int needs_reset;
  93         unsigned bsp_apicid = 0;
  94
  95         if (!cpu_init_detectedx && boot_cpu()) {
  96                 /* Nothing special needs to be done to find bus 0 */
  97                 /* Allow the HT devices to be found */
  98                 enumerate_ht_chain();
  99         }
 100
 101         if (bist == 0)
 102                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 103
 104         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 105         uart_init();
 106         console_init();
 107
 108         /* Halt if there was a built in self test failure */
 109         report_bist_failure(bist);
 110
 111         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 112
 113         setup_default_resource_map();
 114
 115         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 116
 117 #if CONFIG_MEM_TRAIN_SEQ == 1
 118         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 119 #endif
 120         setup_coherent_ht_domain(); // routing table and start other core0
 121
 122         wait_all_core0_started();
 123 #if CONFIG_LOGICAL_CPUS==1
 124         // It is said that we should start core1 after all core0 launched
 125         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 126          * So here need to make sure last core0 is started, esp for two way system,
 127          * (there may be apic id conflicts in that case)
 128          */
 129         start_other_cores();
 130         wait_all_other_cores_started(bsp_apicid);
 131 #endif
 132
 133         /* it will set up chains and store link pair for optimization later */
 134         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 135
 136 #if CONFIG_SET_FIDVID
 137         {
 138                 msr_t msr;
 139                 msr=rdmsr(0xc0010042);
 140                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 141         }
 142         enable_fid_change();
 143         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 144         init_fidvid_bsp(bsp_apicid);
 145         // show final fid and vid
 146         {
 147                 msr_t msr;
 148                 msr=rdmsr(0xc0010042);
 149                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 150         }
 151 #endif
 152
 153         needs_reset = optimize_link_coherent_ht();
 154         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 155
 156         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 157         if (needs_reset) {
 158                 print_info("ht reset -\n");
 159                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 160         }
 161
 162         allow_all_aps_stop(bsp_apicid);
 163
 164         //It's the time to set ctrl in sysinfo now;
 165         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 166
 167         enable_smbus();
 168
 169 #if 0
 170         dump_smbus_registers();
 171 #endif
 172
 173         memreset_setup();
 174
 175         //do we need apci timer, tsc...., only debug need it for better output
 176         /* all ap stopped? */
 177         init_timer(); // Need to use TMICT to synconize FID/VID
 178         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 179
 180 #if 0
 181         dump_pci_devices();
 182 #endif
 183
 184         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 185 }