src/mainboard/iwill/dk8x/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_SCAN_PCI_BUS 1
  14 //#define K8_ALLOCATE_IO_RANGE 1
  15
  16
  17 //used by init_cpus and fidvid
  18 #define K8_SET_FIDVID 0
  19 //if we want to wait for core1 done before DQS training, set it to 0
  20 #define K8_SET_FIDVID_CORE0_ONLY 1
  21
  22 #if K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include "option_table.h"
  35 #include "pc80/mc146818rtc_early.c"
  36
  37 #if USE_FAILOVER_IMAGE==0
  38 #include "pc80/serial.c"
  39 #include "arch/i386/lib/console.c"
  40 #include <cpu/amd/model_fxx_rev.h>
  41 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #endif
  45
  46
  47
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50
  51 #if USE_FAILOVER_IMAGE==0
  52 #include "cpu/x86/bist.h"
  53
  54 #include "lib/delay.c"
  55
  56 #include "northbridge/amd/amdk8/debug.c"
  57 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  58 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  59
  60 #include "northbridge/amd/amdk8/setup_resource_map.c"
  61
  62 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  63
  64 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  65
  66 /*
  67  * GPIO28 of 8111 will control H0_MEMRESET_L
  68  * GPIO29 of 8111 will control H1_MEMRESET_L
  69  */
  70 static void memreset_setup(void)
  71 {
  72         if (is_cpu_pre_c0()) {
  73                 /* Set the memreset low */
  74                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  75                 /* Ensure the BIOS has control of the memory lines */
  76                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  77         } else {
  78                 /* Ensure the CPU has controll of the memory lines */
  79                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  80         }
  81 }
  82
  83 static void memreset(int controllers, const struct mem_controller *ctrl)
  84 {
  85         if (is_cpu_pre_c0()) {
  86                 udelay(800);
  87                 /* Set memreset_high */
  88                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  89                 udelay(90);
  90         }
  91 }
  92
  93 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  94 {
  95 }
  96
  97 static inline int spd_read_byte(unsigned device, unsigned address)
  98 {
  99         return smbus_read_byte(device, address);
 100 }
 101
 102 #include "northbridge/amd/amdk8/amdk8.h"
 103 #include "northbridge/amd/amdk8/coherent_ht.c"
 104
 105 #include "northbridge/amd/amdk8/incoherent_ht.c"
 106
 107 #include "northbridge/amd/amdk8/raminit.c"
 108
 109 #include "sdram/generic_sdram.c"
 110 #include "ram/ramtest.c"
 111
 112  /* tyan does not want the default */
 113 #include "northbridge/amd/amdk8/resourcemap.c"
 114
 115 #include "cpu/amd/dualcore/dualcore.c"
 116
 117 #define DIMM0 0x50
 118 #define DIMM1 0x51
 119 #define DIMM2 0x52
 120 #define DIMM3 0x53
 121 #define DIMM4 0x54
 122 #define DIMM5 0x55
 123 #define DIMM6 0x56
 124 #define DIMM7 0x57
 125
 126
 127 #include "cpu/amd/car/copy_and_run.c"
 128 #include "cpu/amd/car/post_cache_as_ram.c"
 129
 130 #include "cpu/amd/model_fxx/init_cpus.c"
 131
 132 #include "cpu/amd/model_fxx/fidvid.c"
 133 #endif
 134
 135 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 136
 137 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 138 #include "northbridge/amd/amdk8/early_ht.c"
 139
 140 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 141 {
 142
 143         unsigned last_boot_normal_x = last_boot_normal();
 144
 145         /* Is this a cpu only reset? or Is this a secondary cpu? */
 146         if ((cpu_init_detectedx) || (!boot_cpu())) {
 147                 if (last_boot_normal_x) {
 148                         goto normal_image;
 149                 } else {
 150                         goto fallback_image;
 151                 }
 152         }
 153
 154         /* Nothing special needs to be done to find bus 0 */
 155         /* Allow the HT devices to be found */
 156
 157         enumerate_ht_chain();
 158
 159         /* Setup the rom access for 4M */
 160         amd8111_enable_rom();
 161
 162         /* Is this a deliberate reset by the bios */
 163         if (bios_reset_detected() && last_boot_normal_x) {
 164                 goto normal_image;
 165         }
 166         /* This is the primary cpu how should I boot? */
 167         else if (do_normal_boot()) {
 168                 goto normal_image;
 169         }
 170         else {
 171                 goto fallback_image;
 172         }
 173  normal_image:
 174         __asm__ volatile ("jmp __normal_image"
 175                 : /* outputs */
 176                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 177                 );
 178
 179  fallback_image:
 180 #if HAVE_FAILOVER_BOOT==1
 181         __asm__ volatile ("jmp __fallback_image"
 182                 : /* outputs */
 183                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 184                 )
 185 #endif
 186         ;
 187 }
 188 #endif
 189
 190 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 191
 192 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 193 {
 194 #if HAVE_FAILOVER_BOOT==1
 195     #if USE_FAILOVER_IMAGE==1
 196         failover_process(bist, cpu_init_detectedx);
 197     #else
 198         real_main(bist, cpu_init_detectedx);
 199     #endif
 200 #else
 201     #if USE_FALLBACK_IMAGE == 1
 202         failover_process(bist, cpu_init_detectedx);
 203     #endif
 204         real_main(bist, cpu_init_detectedx);
 205 #endif
 206 }
 207
 208 #if USE_FAILOVER_IMAGE==0
 209
 210 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 211 {
 212         static const uint16_t spd_addr[] = {
 213                         //first node
 214                         DIMM0, DIMM2, 0, 0,
 215                         DIMM1, DIMM3, 0, 0,
 216 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 217                         //second node
 218                         DIMM4, DIMM6, 0, 0,
 219                         DIMM5, DIMM7, 0, 0,
 220 #endif
 221
 222         };
 223
 224         struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 225
 226         int needs_reset; int i;
 227         unsigned bsp_apicid = 0;
 228
 229         if (bist == 0) {
 230                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 231         }
 232
 233         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 234         uart_init();
 235         console_init();
 236
 237         /* Halt if there was a built in self test failure */
 238         report_bist_failure(bist);
 239
 240         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 241
 242         setup_default_resource_map();
 243
 244         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 245
 246 #if MEM_TRAIN_SEQ == 1
 247         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 248 #endif
 249         setup_coherent_ht_domain(); // routing table and start other core0
 250
 251         wait_all_core0_started();
 252 #if CONFIG_LOGICAL_CPUS==1
 253         // It is said that we should start core1 after all core0 launched
 254         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 255          * So here need to make sure last core0 is started, esp for two way system,
 256          * (there may be apic id conflicts in that case)
 257          */
 258         start_other_cores();
 259         wait_all_other_cores_started(bsp_apicid);
 260 #endif
 261
 262         /* it will set up chains and store link pair for optimization later */
 263         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 264
 265
 266 #if K8_SET_FIDVID == 1
 267
 268         {
 269                 msr_t msr;
 270                 msr=rdmsr(0xc0010042);
 271                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 272
 273         }
 274
 275         enable_fid_change();
 276
 277         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 278
 279         init_fidvid_bsp(bsp_apicid);
 280
 281         // show final fid and vid
 282         {
 283                 msr_t msr;
 284                 msr=rdmsr(0xc0010042);
 285                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 286
 287         }
 288 #endif
 289
 290         needs_reset = optimize_link_coherent_ht();
 291         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 292
 293         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 294         if (needs_reset) {
 295                 print_info("ht reset -\r\n");
 296                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 297         }
 298
 299         allow_all_aps_stop(bsp_apicid);
 300
 301         //It's the time to set ctrl in sysinfo now;
 302         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 303
 304         enable_smbus();
 305
 306 #if 0
 307         dump_smbus_registers();
 308 #endif
 309
 310         memreset_setup();
 311
 312         //do we need apci timer, tsc...., only debug need it for better output
 313         /* all ap stopped? */
 314         init_timer(); // Need to use TMICT to synconize FID/VID
 315         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 316
 317
 318 #if 0
 319         dump_pci_devices();
 320 #endif
 321
 322         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 323
 324 }
 325 #endif