1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
20 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_XIP_ROM_SIZE
23 uses CONFIG_XIP_ROM_BASE
24 uses CONFIG_STACK_SIZE
26 uses CONFIG_USE_OPTION_TABLE
27 uses CONFIG_LB_CKS_RANGE_START
28 uses CONFIG_LB_CKS_RANGE_END
29 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_MAINBOARD_PART_NUMBER
32 uses CONFIG_MAINBOARD_VENDOR
33 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
35 uses COREBOOT_EXTRA_VERSION
37 uses CONFIG_TTYS0_BAUD
38 uses CONFIG_TTYS0_BASE
40 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
41 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
42 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
43 uses CONFIG_CONSOLE_SERIAL8250
44 uses CONFIG_HAVE_INIT_TIMER
46 uses CONFIG_CROSS_COMPILE
50 uses CONFIG_USE_DCACHE_RAM
51 uses CONFIG_DCACHE_RAM_BASE
52 uses CONFIG_DCACHE_RAM_SIZE
54 uses CONFIG_USE_PRINTK_IN_CAR
56 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
57 default CONFIG_ROM_SIZE=524288
64 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
66 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
69 ## Build code for the fallback boot
71 default CONFIG_HAVE_FALLBACK_BOOT=1
74 ## Build code to reset the motherboard from coreboot
76 default CONFIG_HAVE_HARD_RESET=1
79 ## Build code to export a programmable irq routing table
81 default CONFIG_GENERATE_PIRQ_TABLE=1
82 default CONFIG_IRQ_SLOT_COUNT=12
85 ## Build code to export an x86 MP table
86 ## Useful for specifying IRQ routing values
88 default CONFIG_GENERATE_MP_TABLE=1
91 ## Build code to export a CMOS option table
93 default CONFIG_HAVE_OPTION_TABLE=1
96 ## Move the default coreboot cmos range off of AMD RTC registers
98 default CONFIG_LB_CKS_RANGE_START=49
99 default CONFIG_LB_CKS_RANGE_END=122
100 default CONFIG_LB_CKS_LOC=123
103 ## Build code for SMP support
104 ## Only worry about 2 micro processors
107 default CONFIG_MAX_CPUS=2
108 default CONFIG_MAX_PHYSICAL_CPUS=2
111 ## Build code to setup a generic IOAPIC
113 default CONFIG_IOAPIC=1
116 ## enable CACHE_AS_RAM specifics
118 default CONFIG_USE_DCACHE_RAM=1
119 default CONFIG_DCACHE_RAM_BASE=0xcf000
120 default CONFIG_DCACHE_RAM_SIZE=0x1000
121 default CONFIG_USE_INIT=0
124 ## Clean up the motherboard id strings
126 default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
127 default CONFIG_MAINBOARD_VENDOR="ARIMA"
128 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
129 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
133 ### coreboot layout values
136 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
137 default CONFIG_ROM_IMAGE_SIZE = 65536
140 ## Use a small 8K stack
142 default CONFIG_STACK_SIZE=0x2000
145 ## Use a small 16K heap
147 default CONFIG_HEAP_SIZE=0x4000
150 ## Only use the option table in a normal image
152 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
155 ## Coreboot C code runs at this location in RAM
157 default CONFIG_RAMBASE=0x00004000
160 ## Load the payload from the ROM
162 default CONFIG_ROM_PAYLOAD = 1
165 ### Defaults of options that you may want to override in the target config file
169 ## The default compiler
171 #default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
172 #default HOSTCC="gcc"
175 ## Disable the gdb stub by default
177 default CONFIG_GDB_STUB=0
179 default CONFIG_USE_PRINTK_IN_CAR=1
182 ## The Serial Console
185 # To Enable the Serial Console
186 default CONFIG_CONSOLE_SERIAL8250=1
188 ## Select the serial console baud rate
189 default CONFIG_TTYS0_BAUD=115200
190 #default CONFIG_TTYS0_BAUD=57600
191 #default CONFIG_TTYS0_BAUD=38400
192 #default CONFIG_TTYS0_BAUD=19200
193 #default CONFIG_TTYS0_BAUD=9600
194 #default CONFIG_TTYS0_BAUD=4800
195 #default CONFIG_TTYS0_BAUD=2400
196 #default CONFIG_TTYS0_BAUD=1200
198 # Select the serial console base port
199 default CONFIG_TTYS0_BASE=0x3f8
201 # Select the serial protocol
202 # This defaults to 8 data bits, 1 stop bit, and no parity
203 default CONFIG_TTYS0_LCS=0x3
206 ### Select the coreboot loglevel
208 ## EMERG 1 system is unusable
209 ## ALERT 2 action must be taken immediately
210 ## CRIT 3 critical conditions
211 ## ERR 4 error conditions
212 ## WARNING 5 warning conditions
213 ## NOTICE 6 normal but significant condition
214 ## INFO 7 informational
215 ## CONFIG_DEBUG 8 debug-level messages
216 ## SPEW 9 Way too many details
218 ## Request this level of debugging output
219 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
220 ## At a maximum only compile in this level of debugging
221 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
224 ## Select power on after power fail setting
225 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"