src/mainboard/iwill/dk8s2/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 ## ATI Rage XL framebuffering graphics driver
  51 dir /drivers/ati/ragexl
  52
  53 ##
  54 ## Romcc output
  55 ##
  56 makerule ./failover.E
  57         depends "$(MAINBOARD)/failover.c ./romcc"
  58         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  59 end
  60
  61 makerule ./failover.inc
  62         depends "$(MAINBOARD)/failover.c ./romcc"
  63         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  64 end
  65
  66 makerule ./auto.E
  67         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  68         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  69 end
  70 makerule ./auto.inc
  71         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  72         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  73 end
  74
  75 ##
  76 ## Build our 16 bit and 32 bit linuxBIOS entry code
  77 ##
  78 mainboardinit cpu/x86/16bit/entry16.inc
  79 mainboardinit cpu/x86/32bit/entry32.inc
  80 ldscript /cpu/x86/16bit/entry16.lds
  81 ldscript /cpu/x86/32bit/entry32.lds
  82
  83 ##
  84 ## Build our reset vector (This is where linuxBIOS is entered)
  85 ##
  86 if USE_FALLBACK_IMAGE
  87         mainboardinit cpu/x86/16bit/reset16.inc
  88         ldscript /cpu/x86/16bit/reset16.lds
  89 else
  90         mainboardinit cpu/x86/32bit/reset32.inc
  91         ldscript /cpu/x86/32bit/reset32.lds
  92 end
  93
  94 ### Should this be in the northbridge code?
  95 mainboardinit arch/i386/lib/cpu_reset.inc
  96
  97 ##
  98 ## Include an id string (For safe flashing)
  99 ##
 100 mainboardinit arch/i386/lib/id.inc
 101 ldscript /arch/i386/lib/id.lds
 102
 103 ###
 104 ### This is the early phase of linuxBIOS startup
 105 ### Things are delicate and we test to see if we should
 106 ### failover to another image.
 107 ###
 108 if USE_FALLBACK_IMAGE
 109         ldscript /arch/i386/lib/failover.lds
 110         mainboardinit ./failover.inc
 111 end
 112
 113 ###
 114 ### O.k. We aren't just an intermediary anymore!
 115 ###
 116
 117 ##
 118 ## Setup RAM
 119 ##
 120 mainboardinit cpu/x86/fpu/enable_fpu.inc
 121 mainboardinit cpu/x86/mmx/enable_mmx.inc
 122 mainboardinit cpu/x86/sse/enable_sse.inc
 123 mainboardinit ./auto.inc
 124 mainboardinit cpu/x86/sse/disable_sse.inc
 125 mainboardinit cpu/x86/mmx/disable_mmx.inc
 126
 127 ##
 128 ## Include the secondary Configuration files
 129 ##
 130 dir /pc80
 131 config chip.h
 132
 133 # config for iwill/dk8s2
 134 chip northbridge/amd/amdk8/root_complex
 135         device pci_domain 0 on
 136                 chip northbridge/amd/amdk8
 137                         device pci 18.0 on # LDT 0
 138                                 chip southbridge/amd/amd8131
 139                                         device pci 0.0 on end
 140                                         device pci 0.1 on end
 141                                         device pci 1.0 on end
 142                                         device pci 1.1 on end
 143                                 end
 144                                 chip southbridge/amd/amd8111
 145                                         # this "device pci 0.0" is the parent the next one
 146                                         # PCI bridge
 147                                         device pci 0.0 on
 148                                                 device pci 0.0 on end
 149                                                 device pci 0.1 on end
 150                                                 device pci 0.2 on end
 151                                                 device pci 1.0 off end
 152                                         end
 153                                         device pci 1.0 on
 154                                                 chip superio/winbond/w83627hf
 155                                                         device pnp  2e.0 on      # Floppy
 156                                                                  io 0x60 = 0x3f0
 157                                                                 irq 0x70 = 6
 158                                                                 drq 0x74 = 2
 159                                                         end
 160                                                         device pnp  2e.1 off     # Parallel Port
 161                                                                  io 0x60 = 0x378
 162                                                                 irq 0x70 = 7
 163                                                         end
 164                                                         device pnp  2e.2 on      # Com1
 165                                                                  io 0x60 = 0x3f8
 166                                                                 irq 0x70 = 4
 167                                                         end
 168                                                         device pnp  2e.3 off     # Com2
 169                                                                 io 0x60 = 0x2f8
 170                                                                 irq 0x70 = 3
 171                                                         end
 172                                                         device pnp  2e.5 on      # Keyboard
 173                                                                  io 0x60 = 0x60
 174                                                                  io 0x62 = 0x64
 175                                                                irq 0x70 = 1
 176                                                                 irq 0x72 = 12
 177                                                         end
 178                                                         device pnp  2e.6 off end # CIR
 179                                                         device pnp  2e.7 off end # GAME_MIDI_GIPO1
 180                                                         device pnp  2e.8 off end # GPIO2
 181                                                         device pnp  2e.9 off end # GPIO3
 182                                                         device pnp  2e.a off end # ACPI
 183                                                         device pnp  2e.b on      # HW Monitor
 184                                                                  io 0x60 = 0x290
 185                                                         end
 186                                                         register "com1" = "{1}"
 187                                                 #       register "com1" = "{1, 0, 0x3f8, 4}"
 188                                                 #       register "lpt" = "{1}"
 189                                                 end
 190                                         end
 191                                         device pci 1.1 on end
 192                                         device pci 1.2 on end
 193                                         device pci 1.3 on end
 194                                         device pci 1.5 off end
 195                                         device pci 1.6 off end
 196                                 end
 197                         end # LDT0
 198                         device pci 18.0 on end # LDT1
 199                         device pci 18.0 on end # LDT2
 200                         device pci 18.1 on end
 201                         device pci 18.2 on end
 202                         device pci 18.3 on end
 203                 end
 204                 chip northbridge/amd/amdk8
 205                         device pci 19.0 on end
 206                         device pci 19.0 on end
 207                         device pci 19.0 on end
 208                         device pci 19.1 on end
 209                         device pci 19.2 on end
 210                         device pci 19.3 on end
 211                 end
 212         end
 213         device apic_cluster 0 on
 214                 chip cpu/amd/socket_940
 215                         device apic 0 on end
 216                 end
 217                 chip cpu/amd/socket_940
 218                         device apic 1 on end
 219                 end
 220         end
 221 end
 222