src/mainboard/iwill/dk8_htx/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14
  15 #include <console/console.h>
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23
  24 #include "cpu/x86/bist.h"
  25
  26 #include "lib/delay.c"
  27
  28 #include "northbridge/amd/amdk8/debug.c"
  29 #include "cpu/x86/mtrr/earlymtrr.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "northbridge/amd/amdk8/setup_resource_map.c"
  33
  34 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  35
  36 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  37
  38 /*
  39  * GPIO28 of 8111 will control H0_MEMRESET_L
  40  * GPIO29 of 8111 will control H1_MEMRESET_L
  41  */
  42 static void memreset_setup(void)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 /* Set the memreset low */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  47                 /* Ensure the BIOS has control of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  49         } else {
  50                 /* Ensure the CPU has controll of the memory lines */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  52         }
  53 }
  54
  55 static void memreset(int controllers, const struct mem_controller *ctrl)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 udelay(800);
  59                 /* Set memreset_high */
  60                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  61                 udelay(90);
  62         }
  63 }
  64
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 static inline int spd_read_byte(unsigned device, unsigned address)
  70 {
  71         return smbus_read_byte(device, address);
  72 }
  73
  74 #include "northbridge/amd/amdk8/amdk8.h"
  75 #include "northbridge/amd/amdk8/incoherent_ht.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "northbridge/amd/amdk8/raminit.c"
  78 #include "lib/generic_sdram.c"
  79
  80  /* tyan does not want the default */
  81 #include "resourcemap.c"
  82
  83 #include "cpu/amd/dualcore/dualcore.c"
  84 #include <spd.h>
  85
  86 #include "cpu/amd/car/post_cache_as_ram.c"
  87
  88 #include "cpu/amd/model_fxx/init_cpus.c"
  89
  90 #include "cpu/amd/model_fxx/fidvid.c"
  91
  92 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  93 #include "northbridge/amd/amdk8/early_ht.c"
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const uint16_t spd_addr[] = {
  98                         // first node
  99                         DIMM0, DIMM2, 0, 0,
 100                         DIMM1, DIMM3, 0, 0,
 101
 102                         // second node
 103                         DIMM4, DIMM6, 0, 0,
 104                         DIMM5, DIMM7, 0, 0,
 105         };
 106
 107         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 108                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 109
 110         int needs_reset;
 111         unsigned bsp_apicid = 0;
 112
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0 */
 115                 /* Allow the HT devices to be found */
 116
 117                 enumerate_ht_chain();
 118
 119                 /* Setup the rom access for 4M */
 120                 amd8111_enable_rom();
 121         }
 122
 123         if (bist == 0) {
 124                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 125         }
 126
 127         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 128         uart_init();
 129         console_init();
 130
 131         /* Halt if there was a built in self test failure */
 132         report_bist_failure(bist);
 133
 134         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 135
 136         setup_mb_resource_map();
 137
 138         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 139
 140 #if CONFIG_MEM_TRAIN_SEQ == 1
 141         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 142 #endif
 143         setup_coherent_ht_domain(); // routing table and start other core0
 144
 145         wait_all_core0_started();
 146 #if CONFIG_LOGICAL_CPUS==1
 147         // It is said that we should start core1 after all core0 launched
 148         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 149          * So here need to make sure last core0 is started, esp for two way system,
 150          * (there may be apic id conflicts in that case)
 151          */
 152         start_other_cores();
 153         wait_all_other_cores_started(bsp_apicid);
 154 #endif
 155
 156         /* it will set up chains and store link pair for optimization later */
 157         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 158
 159 #if CONFIG_SET_FIDVID
 160
 161         {
 162                 msr_t msr;
 163                 msr=rdmsr(0xc0010042);
 164                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 165
 166         }
 167
 168         enable_fid_change();
 169
 170         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 171
 172         init_fidvid_bsp(bsp_apicid);
 173
 174         // show final fid and vid
 175         {
 176                 msr_t msr;
 177                 msr=rdmsr(0xc0010042);
 178                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 179
 180         }
 181 #endif
 182
 183         needs_reset = optimize_link_coherent_ht();
 184         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 185
 186         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 187         if (needs_reset) {
 188                 print_info("ht reset -\n");
 189                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 190         }
 191
 192         allow_all_aps_stop(bsp_apicid);
 193
 194         //It's the time to set ctrl in sysinfo now;
 195         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 196
 197         enable_smbus();
 198
 199 #if 0
 200         dump_smbus_registers();
 201 #endif
 202
 203         memreset_setup();
 204
 205         //do we need apci timer, tsc...., only debug need it for better output
 206         /* all ap stopped? */
 207         init_timer(); // Need to use TMICT to synconize FID/VID
 208         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 209
 210 #if 0
 211         dump_pci_devices();
 212 #endif
 213
 214         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 215
 216 }
 217