src/mainboard/iwill/dk8_htx/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   3
   4 #define SET_NB_CFG_54 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 //used by incoherent_ht
  10 //#define K8_ALLOCATE_IO_RANGE 1
  11
  12 //used by init_cpus and fidvid
  13 #define SET_FIDVID 0
  14 //if we want to wait for core1 done before DQS training, set it to 0
  15 #define SET_FIDVID_CORE0_ONLY 1
  16
  17 #if CONFIG_K8_REV_F_SUPPORT == 1
  18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  19 #endif
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include "option_table.h"
  30 #include "pc80/mc146818rtc_early.c"
  31
  32 #include "pc80/serial.c"
  33 #include "console/console.c"
  34 #include <cpu/amd/model_fxx_rev.h>
  35 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41
  42 #include "cpu/x86/bist.h"
  43
  44 #include "lib/delay.c"
  45
  46 #include "northbridge/amd/amdk8/debug.c"
  47 #include "cpu/x86/mtrr/earlymtrr.c"
  48 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  49
  50 #include "northbridge/amd/amdk8/setup_resource_map.c"
  51
  52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  53
  54 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  55
  56 /*
  57  * GPIO28 of 8111 will control H0_MEMRESET_L
  58  * GPIO29 of 8111 will control H1_MEMRESET_L
  59  */
  60 static void memreset_setup(void)
  61 {
  62         if (is_cpu_pre_c0()) {
  63                 /* Set the memreset low */
  64                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  65                 /* Ensure the BIOS has control of the memory lines */
  66                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  67         } else {
  68                 /* Ensure the CPU has controll of the memory lines */
  69                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  70         }
  71 }
  72
  73 static void memreset(int controllers, const struct mem_controller *ctrl)
  74 {
  75         if (is_cpu_pre_c0()) {
  76                 udelay(800);
  77                 /* Set memreset_high */
  78                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  79                 udelay(90);
  80         }
  81 }
  82
  83 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  84 {
  85 }
  86
  87 static inline int spd_read_byte(unsigned device, unsigned address)
  88 {
  89         return smbus_read_byte(device, address);
  90 }
  91
  92 #include "northbridge/amd/amdk8/amdk8.h"
  93 #include "northbridge/amd/amdk8/incoherent_ht.c"
  94 #include "northbridge/amd/amdk8/coherent_ht.c"
  95 #include "northbridge/amd/amdk8/raminit.c"
  96 #include "lib/generic_sdram.c"
  97 #include "lib/ramtest.c"
  98
  99  /* tyan does not want the default */
 100 #include "resourcemap.c"
 101
 102 #include "cpu/amd/dualcore/dualcore.c"
 103
 104 #define DIMM0 0x50
 105 #define DIMM1 0x51
 106 #define DIMM2 0x52
 107 #define DIMM3 0x53
 108 #define DIMM4 0x54
 109 #define DIMM5 0x55
 110 #define DIMM6 0x56
 111 #define DIMM7 0x57
 112
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117 #include "cpu/amd/model_fxx/fidvid.c"
 118
 119 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 123 {
 124         static const uint16_t spd_addr[] = {
 125                         // first node
 126                         DIMM0, DIMM2, 0, 0,
 127                         DIMM1, DIMM3, 0, 0,
 128
 129                         // second node
 130                         DIMM4, DIMM6, 0, 0,
 131                         DIMM5, DIMM7, 0, 0,
 132         };
 133
 134         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 135                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 136
 137         int needs_reset;
 138         unsigned bsp_apicid = 0;
 139
 140         if (!cpu_init_detectedx && boot_cpu()) {
 141                 /* Nothing special needs to be done to find bus 0 */
 142                 /* Allow the HT devices to be found */
 143
 144                 enumerate_ht_chain();
 145
 146                 /* Setup the rom access for 4M */
 147                 amd8111_enable_rom();
 148         }
 149
 150         if (bist == 0) {
 151                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 152         }
 153
 154         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 155         uart_init();
 156         console_init();
 157
 158         /* Halt if there was a built in self test failure */
 159         report_bist_failure(bist);
 160
 161         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 162
 163         setup_mb_resource_map();
 164
 165         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 166
 167 #if CONFIG_MEM_TRAIN_SEQ == 1
 168         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 169 #endif
 170         setup_coherent_ht_domain(); // routing table and start other core0
 171
 172         wait_all_core0_started();
 173 #if CONFIG_LOGICAL_CPUS==1
 174         // It is said that we should start core1 after all core0 launched
 175         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 176          * So here need to make sure last core0 is started, esp for two way system,
 177          * (there may be apic id conflicts in that case)
 178          */
 179         start_other_cores();
 180         wait_all_other_cores_started(bsp_apicid);
 181 #endif
 182
 183         /* it will set up chains and store link pair for optimization later */
 184         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 185
 186 #if SET_FIDVID == 1
 187
 188         {
 189                 msr_t msr;
 190                 msr=rdmsr(0xc0010042);
 191                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 192
 193         }
 194
 195         enable_fid_change();
 196
 197         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 198
 199         init_fidvid_bsp(bsp_apicid);
 200
 201         // show final fid and vid
 202         {
 203                 msr_t msr;
 204                 msr=rdmsr(0xc0010042);
 205                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 206
 207         }
 208 #endif
 209
 210         needs_reset = optimize_link_coherent_ht();
 211         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 212
 213         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 214         if (needs_reset) {
 215                 print_info("ht reset -\n");
 216                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 217         }
 218
 219         allow_all_aps_stop(bsp_apicid);
 220
 221         //It's the time to set ctrl in sysinfo now;
 222         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 223
 224         enable_smbus();
 225
 226 #if 0
 227         dump_smbus_registers();
 228 #endif
 229
 230         memreset_setup();
 231
 232         //do we need apci timer, tsc...., only debug need it for better output
 233         /* all ap stopped? */
 234         init_timer(); // Need to use TMICT to synconize FID/VID
 235         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 236
 237 #if 0
 238         dump_pci_devices();
 239 #endif
 240
 241         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 242
 243 }
 244