src/mainboard/iwill/dk8_htx/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by incoherent_ht
   4 //#define K8_ALLOCATE_IO_RANGE 1
   5
   6 //used by init_cpus and fidvid
   7 #define SET_FIDVID 0
   8 //if we want to wait for core1 done before DQS training, set it to 0
   9 #define SET_FIDVID_CORE0_ONLY 1
  10
  11 #if CONFIG_K8_REV_F_SUPPORT == 1
  12 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  13 #endif
  14
  15 #include <stdint.h>
  16 #include <string.h>
  17 #include <device/pci_def.h>
  18 #include <device/pci_ids.h>
  19 #include <arch/io.h>
  20 #include <device/pnp_def.h>
  21 #include <arch/romcc_io.h>
  22 #include <cpu/x86/lapic.h>
  23 #include <pc80/mc146818rtc.h>
  24
  25 #include <console/console.h>
  26 #include <cpu/amd/model_fxx_rev.h>
  27 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  28 #include "northbridge/amd/amdk8/raminit.h"
  29 #include "cpu/amd/model_fxx/apic_timer.c"
  30
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/amd/amdk8/reset_test.c"
  33
  34 #include "cpu/x86/bist.h"
  35
  36 #include "lib/delay.c"
  37
  38 #include "northbridge/amd/amdk8/debug.c"
  39 #include "cpu/x86/mtrr/earlymtrr.c"
  40 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  41
  42 #include "northbridge/amd/amdk8/setup_resource_map.c"
  43
  44 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  45
  46 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  47
  48 /*
  49  * GPIO28 of 8111 will control H0_MEMRESET_L
  50  * GPIO29 of 8111 will control H1_MEMRESET_L
  51  */
  52 static void memreset_setup(void)
  53 {
  54         if (is_cpu_pre_c0()) {
  55                 /* Set the memreset low */
  56                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  57                 /* Ensure the BIOS has control of the memory lines */
  58                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  59         } else {
  60                 /* Ensure the CPU has controll of the memory lines */
  61                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  62         }
  63 }
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67         if (is_cpu_pre_c0()) {
  68                 udelay(800);
  69                 /* Set memreset_high */
  70                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  71                 udelay(90);
  72         }
  73 }
  74
  75 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  76 {
  77 }
  78
  79 static inline int spd_read_byte(unsigned device, unsigned address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/amdk8.h"
  85 #include "northbridge/amd/amdk8/incoherent_ht.c"
  86 #include "northbridge/amd/amdk8/coherent_ht.c"
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "lib/generic_sdram.c"
  89
  90  /* tyan does not want the default */
  91 #include "resourcemap.c"
  92
  93 #include "cpu/amd/dualcore/dualcore.c"
  94
  95 #define DIMM0 0x50
  96 #define DIMM1 0x51
  97 #define DIMM2 0x52
  98 #define DIMM3 0x53
  99 #define DIMM4 0x54
 100 #define DIMM5 0x55
 101 #define DIMM6 0x56
 102 #define DIMM7 0x57
 103
 104 #include "cpu/amd/car/post_cache_as_ram.c"
 105
 106 #include "cpu/amd/model_fxx/init_cpus.c"
 107
 108 #include "cpu/amd/model_fxx/fidvid.c"
 109
 110 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 111 #include "northbridge/amd/amdk8/early_ht.c"
 112
 113 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 114 {
 115         static const uint16_t spd_addr[] = {
 116                         // first node
 117                         DIMM0, DIMM2, 0, 0,
 118                         DIMM1, DIMM3, 0, 0,
 119
 120                         // second node
 121                         DIMM4, DIMM6, 0, 0,
 122                         DIMM5, DIMM7, 0, 0,
 123         };
 124
 125         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 126                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 127
 128         int needs_reset;
 129         unsigned bsp_apicid = 0;
 130
 131         if (!cpu_init_detectedx && boot_cpu()) {
 132                 /* Nothing special needs to be done to find bus 0 */
 133                 /* Allow the HT devices to be found */
 134
 135                 enumerate_ht_chain();
 136
 137                 /* Setup the rom access for 4M */
 138                 amd8111_enable_rom();
 139         }
 140
 141         if (bist == 0) {
 142                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 143         }
 144
 145         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 146         uart_init();
 147         console_init();
 148
 149         /* Halt if there was a built in self test failure */
 150         report_bist_failure(bist);
 151
 152         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 153
 154         setup_mb_resource_map();
 155
 156         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 157
 158 #if CONFIG_MEM_TRAIN_SEQ == 1
 159         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 160 #endif
 161         setup_coherent_ht_domain(); // routing table and start other core0
 162
 163         wait_all_core0_started();
 164 #if CONFIG_LOGICAL_CPUS==1
 165         // It is said that we should start core1 after all core0 launched
 166         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 167          * So here need to make sure last core0 is started, esp for two way system,
 168          * (there may be apic id conflicts in that case)
 169          */
 170         start_other_cores();
 171         wait_all_other_cores_started(bsp_apicid);
 172 #endif
 173
 174         /* it will set up chains and store link pair for optimization later */
 175         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 176
 177 #if SET_FIDVID == 1
 178
 179         {
 180                 msr_t msr;
 181                 msr=rdmsr(0xc0010042);
 182                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 183
 184         }
 185
 186         enable_fid_change();
 187
 188         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 189
 190         init_fidvid_bsp(bsp_apicid);
 191
 192         // show final fid and vid
 193         {
 194                 msr_t msr;
 195                 msr=rdmsr(0xc0010042);
 196                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 197
 198         }
 199 #endif
 200
 201         needs_reset = optimize_link_coherent_ht();
 202         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 203
 204         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 205         if (needs_reset) {
 206                 print_info("ht reset -\n");
 207                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 208         }
 209
 210         allow_all_aps_stop(bsp_apicid);
 211
 212         //It's the time to set ctrl in sysinfo now;
 213         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 214
 215         enable_smbus();
 216
 217 #if 0
 218         dump_smbus_registers();
 219 #endif
 220
 221         memreset_setup();
 222
 223         //do we need apci timer, tsc...., only debug need it for better output
 224         /* all ap stopped? */
 225         init_timer(); // Need to use TMICT to synconize FID/VID
 226         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 227
 228 #if 0
 229         dump_pci_devices();
 230 #endif
 231
 232         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 233
 234 }
 235