src/mainboard/iwill/dk8_htx/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by raminit
   4
   5 //used by incoherent_ht
   6 //#define K8_ALLOCATE_IO_RANGE 1
   7
   8 //used by init_cpus and fidvid
   9 #define SET_FIDVID 0
  10 //if we want to wait for core1 done before DQS training, set it to 0
  11 #define SET_FIDVID_CORE0_ONLY 1
  12
  13 #if CONFIG_K8_REV_F_SUPPORT == 1
  14 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  15 #endif
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <device/pci_def.h>
  20 #include <device/pci_ids.h>
  21 #include <arch/io.h>
  22 #include <device/pnp_def.h>
  23 #include <arch/romcc_io.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <pc80/mc146818rtc.h>
  26
  27 #include <console/console.h>
  28 #include <cpu/amd/model_fxx_rev.h>
  29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35
  36 #include "cpu/x86/bist.h"
  37
  38 #include "lib/delay.c"
  39
  40 #include "northbridge/amd/amdk8/debug.c"
  41 #include "cpu/x86/mtrr/earlymtrr.c"
  42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  43
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  47
  48 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  49
  50 /*
  51  * GPIO28 of 8111 will control H0_MEMRESET_L
  52  * GPIO29 of 8111 will control H1_MEMRESET_L
  53  */
  54 static void memreset_setup(void)
  55 {
  56         if (is_cpu_pre_c0()) {
  57                 /* Set the memreset low */
  58                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  59                 /* Ensure the BIOS has control of the memory lines */
  60                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  61         } else {
  62                 /* Ensure the CPU has controll of the memory lines */
  63                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  64         }
  65 }
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69         if (is_cpu_pre_c0()) {
  70                 udelay(800);
  71                 /* Set memreset_high */
  72                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  73                 udelay(90);
  74         }
  75 }
  76
  77 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  78 {
  79 }
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #include "northbridge/amd/amdk8/amdk8.h"
  87 #include "northbridge/amd/amdk8/incoherent_ht.c"
  88 #include "northbridge/amd/amdk8/coherent_ht.c"
  89 #include "northbridge/amd/amdk8/raminit.c"
  90 #include "lib/generic_sdram.c"
  91
  92  /* tyan does not want the default */
  93 #include "resourcemap.c"
  94
  95 #include "cpu/amd/dualcore/dualcore.c"
  96
  97 #define DIMM0 0x50
  98 #define DIMM1 0x51
  99 #define DIMM2 0x52
 100 #define DIMM3 0x53
 101 #define DIMM4 0x54
 102 #define DIMM5 0x55
 103 #define DIMM6 0x56
 104 #define DIMM7 0x57
 105
 106 #include "cpu/amd/car/post_cache_as_ram.c"
 107
 108 #include "cpu/amd/model_fxx/init_cpus.c"
 109
 110 #include "cpu/amd/model_fxx/fidvid.c"
 111
 112 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 113 #include "northbridge/amd/amdk8/early_ht.c"
 114
 115 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 116 {
 117         static const uint16_t spd_addr[] = {
 118                         // first node
 119                         DIMM0, DIMM2, 0, 0,
 120                         DIMM1, DIMM3, 0, 0,
 121
 122                         // second node
 123                         DIMM4, DIMM6, 0, 0,
 124                         DIMM5, DIMM7, 0, 0,
 125         };
 126
 127         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 128                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 129
 130         int needs_reset;
 131         unsigned bsp_apicid = 0;
 132
 133         if (!cpu_init_detectedx && boot_cpu()) {
 134                 /* Nothing special needs to be done to find bus 0 */
 135                 /* Allow the HT devices to be found */
 136
 137                 enumerate_ht_chain();
 138
 139                 /* Setup the rom access for 4M */
 140                 amd8111_enable_rom();
 141         }
 142
 143         if (bist == 0) {
 144                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 145         }
 146
 147         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 148         uart_init();
 149         console_init();
 150
 151         /* Halt if there was a built in self test failure */
 152         report_bist_failure(bist);
 153
 154         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 155
 156         setup_mb_resource_map();
 157
 158         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 159
 160 #if CONFIG_MEM_TRAIN_SEQ == 1
 161         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 162 #endif
 163         setup_coherent_ht_domain(); // routing table and start other core0
 164
 165         wait_all_core0_started();
 166 #if CONFIG_LOGICAL_CPUS==1
 167         // It is said that we should start core1 after all core0 launched
 168         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 169          * So here need to make sure last core0 is started, esp for two way system,
 170          * (there may be apic id conflicts in that case)
 171          */
 172         start_other_cores();
 173         wait_all_other_cores_started(bsp_apicid);
 174 #endif
 175
 176         /* it will set up chains and store link pair for optimization later */
 177         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 178
 179 #if SET_FIDVID == 1
 180
 181         {
 182                 msr_t msr;
 183                 msr=rdmsr(0xc0010042);
 184                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 185
 186         }
 187
 188         enable_fid_change();
 189
 190         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 191
 192         init_fidvid_bsp(bsp_apicid);
 193
 194         // show final fid and vid
 195         {
 196                 msr_t msr;
 197                 msr=rdmsr(0xc0010042);
 198                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 199
 200         }
 201 #endif
 202
 203         needs_reset = optimize_link_coherent_ht();
 204         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 205
 206         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 207         if (needs_reset) {
 208                 print_info("ht reset -\n");
 209                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 210         }
 211
 212         allow_all_aps_stop(bsp_apicid);
 213
 214         //It's the time to set ctrl in sysinfo now;
 215         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 216
 217         enable_smbus();
 218
 219 #if 0
 220         dump_smbus_registers();
 221 #endif
 222
 223         memreset_setup();
 224
 225         //do we need apci timer, tsc...., only debug need it for better output
 226         /* all ap stopped? */
 227         init_timer(); // Need to use TMICT to synconize FID/VID
 228         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 229
 230 #if 0
 231         dump_pci_devices();
 232 #endif
 233
 234         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 235
 236 }
 237