1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/failovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 #needed by irq_tables and mptable and acpi_tables
18 if CONFIG_GENERATE_MP_TABLE
22 if CONFIG_GENERATE_PIRQ_TABLE
26 #if CONFIG_GENERATE_ACPI_TABLES
27 # object acpi_tables.o
29 # if CONFIG_SB_HT_CHAIN_ON_BUS0
35 # if CONFIG_ACPI_SSDTX_NUM
36 # if CONFIG_SB_HT_CHAIN_ON_BUS0
44 if CONFIG_GENERATE_ACPI_TABLES
48 depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
49 action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
50 action "mv dsdt_lb.hex dsdt.c"
54 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
56 if CONFIG_ACPI_SSDTX_NUM
58 depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
59 action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
60 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
61 action "mv pci2.hex ssdt2.c"
65 depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
66 action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
67 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
68 action "mv pci3.hex ssdt3.c"
72 depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
73 action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
74 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
75 action "mv pci4.hex ssdt4.c"
79 depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
80 action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
81 action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
82 action "mv pci5.hex ssdt5.c"
89 # compile cache_as_ram.c to auto.o
90 makerule ./cache_as_ram_auto.o
91 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
92 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
96 #compile cache_as_ram.c to auto.inc
97 makerule ./cache_as_ram_auto.inc
98 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
99 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
100 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
101 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
106 if CONFIG_USE_FAILOVER_IMAGE
108 if CONFIG_AP_CODE_IN_CAR
109 makerule ./apc_auto.o
110 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
111 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
113 ldscript /arch/i386/init/ldscript_apc.lb
118 ## Build our 16 bit and 32 bit coreboot entry code
121 if CONFIG_HAVE_FAILOVER_BOOT
122 if CONFIG_USE_FAILOVER_IMAGE
123 mainboardinit cpu/x86/16bit/entry16.inc
124 ldscript /cpu/x86/16bit/entry16.lds
127 if CONFIG_USE_FALLBACK_IMAGE
128 mainboardinit cpu/x86/16bit/entry16.inc
129 ldscript /cpu/x86/16bit/entry16.lds
133 mainboardinit cpu/x86/32bit/entry32.inc
135 ldscript /cpu/x86/32bit/entry32.lds
139 ldscript /cpu/amd/car/cache_as_ram.lds
143 ## Build our reset vector (This is where coreboot is entered)
145 if CONFIG_HAVE_FAILOVER_BOOT
146 if CONFIG_USE_FAILOVER_IMAGE
147 mainboardinit cpu/x86/16bit/reset16.inc
148 ldscript /cpu/x86/16bit/reset16.lds
150 mainboardinit cpu/x86/32bit/reset32.inc
151 ldscript /cpu/x86/32bit/reset32.lds
154 if CONFIG_USE_FALLBACK_IMAGE
155 mainboardinit cpu/x86/16bit/reset16.inc
156 ldscript /cpu/x86/16bit/reset16.lds
158 mainboardinit cpu/x86/32bit/reset32.inc
159 ldscript /cpu/x86/32bit/reset32.lds
164 ## Include an id string (For safe flashing)
166 mainboardinit arch/i386/lib/id.inc
167 ldscript /arch/i386/lib/id.lds
170 ## Setup Cache-As-Ram
172 mainboardinit cpu/amd/car/cache_as_ram.inc
175 ### This is the early phase of coreboot startup
176 ### Things are delicate and we test to see if we should
177 ### failover to another image.
179 if CONFIG_HAVE_FAILOVER_BOOT
180 if CONFIG_USE_FAILOVER_IMAGE
181 ldscript /arch/i386/lib/failover_failover.lds
184 if CONFIG_USE_FALLBACK_IMAGE
185 ldscript /arch/i386/lib/failover.lds
190 ### O.k. We aren't just an intermediary anymore!
197 initobject cache_as_ram_auto.o
199 mainboardinit ./cache_as_ram_auto.inc
203 ## Include the secondary Configuration files
207 dir /southbridge/amd/amd8132
209 chip northbridge/amd/amdk8/root_complex
210 device apic_cluster 0 on
211 chip cpu/amd/socket_940
215 device pci_domain 0 on
216 chip northbridge/amd/amdk8
217 device pci 18.0 on end
218 device pci 18.0 on end
219 device pci 18.0 on # northbridge
220 chip southbridge/amd/amd8131
221 # the on/off keyword is mandatory
222 device pci 0.0 on end
223 device pci 0.1 on end
224 device pci 1.0 on end
225 device pci 1.1 on end
227 chip southbridge/amd/amd8111
228 # this "device pci 0.0" is the parent the next one
231 device pci 0.0 on end
232 device pci 0.1 on end
233 device pci 0.2 off end
234 device pci 1.0 off end
237 chip superio/winbond/w83627hf
238 device pnp 2e.0 off # Floppy
243 device pnp 2e.1 off # Parallel Port
247 device pnp 2e.2 on # Com1
251 device pnp 2e.3 off # Com2
255 device pnp 2e.5 on # Keyboard
261 device pnp 2e.6 off # CIR
264 device pnp 2e.7 off # GAME_MIDI_GIPO1
269 device pnp 2e.8 on # GPIO2
275 device pnp 2e.9 off end # GPIO3
276 device pnp 2e.a off end # ACPI
277 device pnp 2e.b on # HW Monitor
283 device pci 1.1 on end
284 device pci 1.2 on end
286 chip drivers/generic/generic #dimm 0-0-0
289 chip drivers/generic/generic #dimm 0-0-1
292 chip drivers/generic/generic #dimm 0-1-0
295 chip drivers/generic/generic #dimm 0-1-1
298 chip drivers/generic/generic #dimm 1-0-0
301 chip drivers/generic/generic #dimm 1-0-1
304 chip drivers/generic/generic #dimm 1-1-0
307 chip drivers/generic/generic #dimm 1-1-1
311 device pci 1.5 off end
312 device pci 1.6 off end
313 register "ide0_enable" = "1"
314 register "ide1_enable" = "1"
316 end # device pci 18.0
318 device pci 18.1 on end
319 device pci 18.2 on end
320 device pci 18.3 on end
324 # chip drivers/generic/debug
325 # device pnp 0.0 off end # chip name
326 # device pnp 0.1 on end # pci_regs_all
327 # device pnp 0.2 off end # mem
328 # device pnp 0.3 off end # cpuid
329 # device pnp 0.4 off end # smbus_regs_all
330 # device pnp 0.5 off end # dual core msr
331 # device pnp 0.6 off end # cache size
332 # device pnp 0.7 off end # tsc