1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
12 if CONFIG_GENERATE_MP_TABLE object mptable.o end
13 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
14 if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o end
15 if CONFIG_HAVE_HARD_RESET object reset.o end
21 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
22 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
25 makerule ./failover.inc
26 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
27 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
31 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
32 action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
35 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
36 action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
40 ## Build our 16 bit and 32 bit coreboot entry code
42 mainboardinit cpu/x86/16bit/entry16.inc
43 mainboardinit cpu/x86/32bit/entry32.inc
44 ldscript /cpu/x86/16bit/entry16.lds
45 ldscript /cpu/x86/32bit/entry32.lds
48 ## Build our reset vector (This is where coreboot is entered)
50 if CONFIG_HAVE_FALLBACK_BOOT
51 if CONFIG_USE_FALLBACK_IMAGE
52 mainboardinit cpu/x86/16bit/reset16.inc
53 ldscript /cpu/x86/16bit/reset16.lds
55 mainboardinit cpu/x86/32bit/reset32.inc
56 ldscript /cpu/x86/32bit/reset32.lds
59 mainboardinit cpu/x86/16bit/reset16.inc
60 ldscript /cpu/x86/16bit/reset16.lds
63 ### Should this be in the northbridge code?
64 mainboardinit arch/i386/lib/cpu_reset.inc
67 ## Include an id string (For safe flashing)
69 mainboardinit arch/i386/lib/id.inc
70 ldscript /arch/i386/lib/id.lds
73 ### This is the early phase of coreboot startup
74 ### Things are delicate and we test to see if we should
75 ### failover to another image.
77 if CONFIG_USE_FALLBACK_IMAGE
78 ldscript /arch/i386/lib/failover.lds
79 mainboardinit ./failover.inc
83 ### O.k. We aren't just an intermediary anymore!
89 mainboardinit cpu/x86/fpu_enable.inc
90 mainboardinit cpu/x86/sse_enable.inc
91 mainboardinit ./auto.inc
92 mainboardinit cpu/x86/sse_disable.inc
93 mainboardinit cpu/x86/mmx_disable.inc
96 ## Include the secondary Configuration files
102 # based on sample config for tyan/s2735
103 chip northbridge/intel/e7501
104 device pci_domain 0 on
105 device pci 0.0 on end # Chipset host controller
106 device pci 0.1 on end # Host RASUM controller
107 device pci 2.0 on # Hub interface B
108 chip southbridge/intel/i82870 # P64H2
109 device pci 1c.0 on end # IOAPIC - bus B
110 device pci 1d.0 on end # Hub to PCI-B bridge
111 device pci 1e.0 on end # IOAPIC - bus A
112 device pci 1f.0 on end # Hub to PCI-A bridge
115 device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
116 device pci 4.0 on # Hub interface D
117 chip southbridge/intel/i82870 # P64H2
118 device pci 1c.0 on end # IOAPIC - bus B
119 device pci 1d.0 on end # Hub to PCI-B bridge
120 device pci 1e.0 on end # IOAPIC - bus A
121 device pci 1f.0 on end # Hub to PCI-A bridge
124 device pci 6.0 on end # E7501 Power management registers? (undocumented)
125 chip southbridge/intel/i82801ca
126 device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
127 device pci 1d.1 off end # USB (not populated)
128 device pci 1d.2 off end # USB (not populated)
129 device pci 1e.0 on # Hub to PCI bridge
130 device pci 0.0 on end
132 device pci 1f.0 on # LPC bridge
133 chip superio/smsc/lpc47b272
134 device pnp 2e.0 off # Floppy
139 device pnp 2e.3 off # Parallel Port
143 device pnp 2e.4 on # Com1
147 device pnp 2e.5 off # Com2
151 device pnp 2e.7 on # Keyboard
154 irq 0x70 = 1 # Keyboard interrupt
155 irq 0x72 = 12 # Mouse interrupt
157 device pnp 2e.a off end # ACPI
160 device pci 1f.1 on end # IDE
161 device pci 1f.3 on end # SMBus
162 device pci 1f.5 off end # AC97 Audio
163 device pci 1f.6 off end # AC97 Modem
166 device apic_cluster 0 on
167 chip cpu/intel/socket_mPGA604
170 chip cpu/intel/socket_mPGA604