src/mainboard/intel/truxton/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <stdint.h>
  21 #include <stdlib.h>
  22 #include <device/pci_def.h>
  23 #include <device/pci_ids.h>
  24 #include <arch/io.h>
  25 #include <device/pnp_def.h>
  26 #include <arch/romcc_io.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <pc80/mc146818rtc.h>
  29 #include "pc80/udelay_io.c"
  30 #include <console/console.h>
  31 #include "lib/ramtest.c"
  32 #include "southbridge/intel/i3100/i3100_early_smbus.c"
  33 #include "southbridge/intel/i3100/i3100_early_lpc.c"
  34 #include "northbridge/intel/i3100/raminit_ep80579.h"
  35 #include "superio/intel/i3100/i3100.h"
  36 #include "cpu/x86/lapic/boot_cpu.c"
  37 #include "cpu/x86/mtrr/earlymtrr.c"
  38 #include "superio/intel/i3100/i3100_early_serial.c"
  39 #include "cpu/x86/bist.h"
  40 #include <spd.h>
  41
  42 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
  43
  44 static inline int spd_read_byte(u16 device, u8 address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 #include "northbridge/intel/i3100/raminit_ep80579.c"
  50 #include "lib/generic_sdram.c"
  51 #include "../../intel/jarrell/debug.c"
  52 #include "arch/i386/lib/stages.c"
  53
  54 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
  55
  56 static void main(unsigned long bist)
  57 {
  58         msr_t msr;
  59         u16 perf;
  60         static const struct mem_controller mch[] = {
  61                 {
  62                         .node_id = 0,
  63                         .f0 = PCI_DEV(0, 0x00, 0),
  64                         .channel0 = { DIMM2, DIMM3 },
  65                 }
  66         };
  67
  68         if (bist == 0) {
  69                 /* Skip this if there was a built in self test failure */
  70                 early_mtrr_init();
  71                 if (memory_initialized()) {
  72                         skip_romstage();
  73                 }
  74         }
  75
  76         /* Set up the console */
  77         i3100_enable_superio();
  78         i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  79         i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
  80
  81         uart_init();
  82         console_init();
  83
  84         /* Prevent the TCO timer from rebooting us */
  85         i3100_halt_tco_timer();
  86
  87         /* Halt if there was a built in self test failure */
  88         report_bist_failure(bist);
  89
  90 #ifdef TRUXTON_DEBUG
  91         print_pci_devices();
  92 #endif
  93         enable_smbus();
  94         dump_spd_registers();
  95
  96         sdram_initialize(ARRAY_SIZE(mch), mch);
  97         dump_pci_devices();
  98         dump_pci_device(PCI_DEV(0, 0x00, 0));
  99 #ifdef TRUXTON_DEBUG
 100         dump_bar14(PCI_DEV(0, 0x00, 0));
 101 #endif
 102
 103 #ifdef TRUXTON_DEBUG
 104         ram_fill(0x00000000, 0x02000000);
 105         ram_verify(0x00000000, 0x02000000);
 106 #endif
 107 }
 108