2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <arch/ioapic.h>
23 #include <device/pci.h>
27 static void *smp_write_config_table(void *v)
29 struct mp_config_table *mc;
37 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
39 mptable_init(mc, "Truxton ", LAPIC_ADDR);
41 smp_write_processors(mc);
44 dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
46 bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
47 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
51 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
56 dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
58 bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
61 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
65 dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
67 bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
70 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
74 /* define bus and isa numbers */
75 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
76 smp_write_bus(mc, bus_num, "PCI ");
78 smp_write_bus(mc, bus_isa, "ISA ");
81 smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
83 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
85 /* Standard local interrupt assignments */
86 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
87 bus_isa, 0x00, MP_APIC_ALL, 0x00);
88 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
89 bus_isa, 0x00, MP_APIC_ALL, 0x01);
91 /* IMCH/IICH PCI devices */
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
93 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
95 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
97 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
99 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
101 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
103 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
108 bus_pea0, (0<<2)|0, 0x8, 0x10);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
110 bus_pea0, (0<<2)|1, 0x8, 0x11);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
112 bus_pea0, (0<<2)|2, 0x8, 0x12);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
114 bus_pea0, (0<<2)|3, 0x8, 0x13);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_pea1, (0<<2)|0, 0x8, 0x10);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_pea1, (0<<2)|1, 0x8, 0x11);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_pea1, (0<<2)|2, 0x8, 0x12);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
126 bus_pea1, (0<<2)|3, 0x8, 0x13);
130 /* AIOC PCI devices */
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
132 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
134 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
136 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
139 /* There is no extension information... */
141 /* Compute the checksums */
142 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
144 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
145 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
146 mc, smp_next_mpe_entry(mc));
147 return smp_next_mpe_entry(mc);
150 unsigned long write_smp_table(unsigned long addr)
153 v = smp_write_floating_table(addr);
154 return (unsigned long)smp_write_config_table(v);