2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <arch/ioapic.h>
23 #include <device/pci.h>
27 static void *smp_write_config_table(void *v)
29 struct mp_config_table *mc;
36 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
38 mptable_init(mc, LAPIC_ADDR);
40 smp_write_processors(mc);
43 dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
45 bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
48 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
52 dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
54 bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
57 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
61 dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
63 bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
66 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
70 mptable_write_buses(mc, NULL, &bus_isa);
73 smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
75 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
77 /* Standard local interrupt assignments */
78 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
79 bus_isa, 0x00, MP_APIC_ALL, 0x00);
80 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
81 bus_isa, 0x00, MP_APIC_ALL, 0x01);
83 /* IMCH/IICH PCI devices */
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
85 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
87 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
89 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
91 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
93 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
95 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
100 bus_pea0, (0<<2)|0, 0x8, 0x10);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
102 bus_pea0, (0<<2)|1, 0x8, 0x11);
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
104 bus_pea0, (0<<2)|2, 0x8, 0x12);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
106 bus_pea0, (0<<2)|3, 0x8, 0x13);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
112 bus_pea1, (0<<2)|0, 0x8, 0x10);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
114 bus_pea1, (0<<2)|1, 0x8, 0x11);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
116 bus_pea1, (0<<2)|2, 0x8, 0x12);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
118 bus_pea1, (0<<2)|3, 0x8, 0x13);
122 /* AIOC PCI devices */
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
126 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
131 /* There is no extension information... */
133 /* Compute the checksums */
134 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
136 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
137 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
138 mc, smp_next_mpe_entry(mc));
139 return smp_next_mpe_entry(mc);
142 unsigned long write_smp_table(unsigned long addr)
145 v = smp_write_floating_table(addr);
146 return (unsigned long)smp_write_config_table(v);