2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
28 #include <cpu/x86/lapic.h>
29 #include "pc80/mc146818rtc_early.c"
30 #include <console/console.h>
31 #include "lib/ramtest.c"
32 #include "southbridge/intel/i3100/i3100_early_smbus.c"
33 #include "southbridge/intel/i3100/i3100_early_lpc.c"
34 #include "northbridge/intel/i3100/raminit.h"
35 #include "superio/intel/i3100/i3100.h"
36 #include "cpu/x86/lapic/boot_cpu.c"
37 #include "cpu/x86/mtrr/earlymtrr.c"
38 #include "superio/intel/i3100/i3100_early_serial.c"
39 #include "northbridge/intel/i3100/memory_initialized.c"
40 #include "cpu/x86/bist.h"
42 #define SIO_GPIO_BASE 0x680
43 #define SIO_XBUS_BASE 0x4880
45 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
46 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
48 static inline int spd_read_byte(u16 device, u8 address)
50 return smbus_read_byte(device, address);
53 #include "northbridge/intel/i3100/raminit.c"
54 #include "lib/generic_sdram.c"
55 #include "../jarrell/debug.c"
56 #include "arch/i386/lib/stages.c"
58 static void main(unsigned long bist)
62 static const struct mem_controller mch[] = {
65 .f0 = PCI_DEV(0, 0x00, 0),
66 .f1 = PCI_DEV(0, 0x00, 1),
67 .f2 = PCI_DEV(0, 0x00, 2),
68 .f3 = PCI_DEV(0, 0x00, 3),
69 .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
70 .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
75 /* Skip this if there was a built in self test failure */
77 if (memory_initialized()) {
81 /* Set up the console */
82 i3100_enable_superio();
83 i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
87 /* Prevent the TCO timer from rebooting us */
88 i3100_halt_tco_timer();
90 /* Halt if there was a built in self test failure */
91 report_bist_failure(bist);
93 /* print_pci_devices(); */
95 /* dump_spd_registers(); */
97 /* Enable SpeedStep and automatic thermal throttling */
98 /* FIXME: move to Pentium M init code */
100 msr.lo |= (1 << 3) | (1 << 16);
106 /* Set CPU frequency/voltage to maximum */
107 /* FIXME: move to Pentium M init code */
109 perf = msr.hi & 0xffff;
111 msr.lo &= 0xffff0000;
115 sdram_initialize(ARRAY_SIZE(mch), mch);
116 /* dump_pci_devices(); */
117 /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
118 /* dump_bar14(PCI_DEV(0, 0x00, 0)); */
120 ram_check(0, 1024 * 1024);