2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
28 #include <cpu/x86/lapic.h>
29 #include "pc80/mc146818rtc_early.c"
30 #include "pc80/serial.c"
31 #include "arch/i386/lib/console.c"
32 #include "lib/ramtest.c"
33 #include "southbridge/intel/i3100/i3100_early_smbus.c"
34 #include "southbridge/intel/i3100/i3100_early_lpc.c"
35 #include "northbridge/intel/i3100/raminit.h"
36 #include "superio/intel/i3100/i3100.h"
37 #include "cpu/x86/lapic/boot_cpu.c"
38 #include "cpu/x86/mtrr/earlymtrr.c"
39 #include "superio/intel/i3100/i3100_early_serial.c"
40 #include "northbridge/intel/i3100/memory_initialized.c"
41 #include "cpu/x86/bist.h"
43 #define SIO_GPIO_BASE 0x680
44 #define SIO_XBUS_BASE 0x4880
46 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
47 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
53 static inline int spd_read_byte(u16 device, u8 address)
55 return smbus_read_byte(device, address);
58 #include "northbridge/intel/i3100/raminit.c"
59 #include "lib/generic_sdram.c"
60 #include "../jarrell/debug.c"
62 static void main(unsigned long bist)
66 static const struct mem_controller mch[] = {
69 .f0 = PCI_DEV(0, 0x00, 0),
70 .f1 = PCI_DEV(0, 0x00, 1),
71 .f2 = PCI_DEV(0, 0x00, 2),
72 .f3 = PCI_DEV(0, 0x00, 3),
73 .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
74 .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
79 /* Skip this if there was a built in self test failure */
81 if (memory_initialized()) {
82 asm volatile ("jmp __cpu_reset");
85 /* Set up the console */
86 i3100_enable_superio();
87 i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE);
91 /* Prevent the TCO timer from rebooting us */
92 i3100_halt_tco_timer();
94 /* Halt if there was a built in self test failure */
95 report_bist_failure(bist);
97 /* print_pci_devices(); */
99 /* dump_spd_registers(); */
101 /* Enable SpeedStep and automatic thermal throttling */
102 /* FIXME: move to Pentium M init code */
104 msr.lo |= (1 << 3) | (1 << 16);
110 /* Set CPU frequency/voltage to maximum */
111 /* FIXME: move to Pentium M init code */
113 perf = msr.hi & 0xffff;
115 msr.lo &= 0xffff0000;
119 sdram_initialize(ARRAY_SIZE(mch), mch);
120 /* dump_pci_devices(); */
121 /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
122 /* dump_bar14(PCI_DEV(0, 0x00, 0)); */
124 ram_check(0, 1024 * 1024);