2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
28 #include <cpu/x86/lapic.h>
29 #include <pc80/mc146818rtc.h>
30 #include <console/console.h>
31 #include "southbridge/intel/i3100/i3100_early_smbus.c"
32 #include "southbridge/intel/i3100/i3100_early_lpc.c"
33 #include "northbridge/intel/i3100/raminit.h"
34 #include "superio/intel/i3100/i3100.h"
35 #include "cpu/x86/mtrr/earlymtrr.c"
36 #include "superio/intel/i3100/i3100_early_serial.c"
37 #include "northbridge/intel/i3100/memory_initialized.c"
38 #include "cpu/x86/bist.h"
41 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
42 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
44 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
46 static inline int spd_read_byte(u16 device, u8 address)
48 return smbus_read_byte(device, address);
51 #include "northbridge/intel/i3100/raminit.c"
52 #include "lib/generic_sdram.c"
53 #if 0 /* skip_romstage doesn't compile with gcc */
54 #include "arch/i386/lib/stages.c"
57 void main(unsigned long bist)
61 static const struct mem_controller mch[] = {
64 .f0 = PCI_DEV(0, 0x00, 0),
65 .f1 = PCI_DEV(0, 0x00, 1),
66 .f2 = PCI_DEV(0, 0x00, 2),
67 .f3 = PCI_DEV(0, 0x00, 3),
68 .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
69 .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
74 #if 0 /* skip_romstage doesn't compile with gcc */
75 /* Skip this if there was a built in self test failure */
76 if (memory_initialized()) {
82 /* Set up the console */
83 i3100_enable_superio();
84 i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
85 i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
90 /* Prevent the TCO timer from rebooting us */
91 i3100_halt_tco_timer();
93 /* Halt if there was a built in self test failure */
94 report_bist_failure(bist);
96 /* print_pci_devices(); */
98 /* dump_spd_registers(); */
100 /* Enable SpeedStep and automatic thermal throttling */
101 /* FIXME: move to Pentium M init code */
103 msr.lo |= (1 << 3) | (1 << 16);
109 /* Set CPU frequency/voltage to maximum */
110 /* FIXME: move to Pentium M init code */
112 perf = msr.hi & 0xffff;
114 msr.lo &= 0xffff0000;
118 sdram_initialize(ARRAY_SIZE(mch), mch);
119 /* dump_pci_devices(); */
120 /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
121 /* dump_bar14(PCI_DEV(0, 0x00, 0)); */
123 ram_check(0, 1024 * 1024);