2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Arastra, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License version 2 as
8 ## published by the Free Software Foundation.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 uses CONFIG_HAVE_MP_TABLE
21 uses CONFIG_HAVE_PIRQ_TABLE
22 uses CONFIG_USE_FALLBACK_IMAGE
23 uses CONFIG_HAVE_FALLBACK_BOOT
24 uses CONFIG_HAVE_HARD_RESET
25 uses CONFIG_IRQ_SLOT_COUNT
26 uses CONFIG_LOGICAL_CPUS
30 uses CONFIG_FALLBACK_SIZE
32 uses CONFIG_ROM_SECTION_SIZE
33 uses CONFIG_ROM_IMAGE_SIZE
34 uses CONFIG_ROM_SECTION_SIZE
35 uses CONFIG_ROM_SECTION_OFFSET
36 uses CONFIG_ROM_PAYLOAD
37 uses CONFIG_ROM_PAYLOAD_START
38 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
39 uses CONFIG_PAYLOAD_SIZE
41 uses CONFIG_XIP_ROM_SIZE
42 uses CONFIG_XIP_ROM_BASE
43 uses CONFIG_STACK_SIZE
45 uses CONFIG_LB_CKS_RANGE_START
46 uses CONFIG_LB_CKS_RANGE_END
47 uses CONFIG_LB_CKS_LOC
49 uses CONFIG_MAINBOARD_PART_NUMBER
50 uses CONFIG_MAINBOARD_VENDOR
51 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
52 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
53 uses COREBOOT_EXTRA_VERSION
54 uses CONFIG_UDELAY_TSC
55 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
58 uses CONFIG_CONSOLE_SERIAL8250
59 uses CONFIG_TTYS0_BAUD
60 uses CONFIG_TTYS0_BASE
62 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
63 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
64 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
67 uses CONFIG_CROSS_COMPILE
76 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
78 default CONFIG_ROM_SIZE = 2 * 1024 * 1024
81 ## Build code for the fallback boot
83 default CONFIG_HAVE_FALLBACK_BOOT=1
86 ## Delay timer options
89 default CONFIG_UDELAY_TSC=1
90 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
93 ## Build code to reset the motherboard from coreboot
95 default CONFIG_HAVE_HARD_RESET=1
98 ## Build code to export a programmable irq routing table
100 default CONFIG_HAVE_PIRQ_TABLE=1
101 default CONFIG_IRQ_SLOT_COUNT=1
104 ## Build code to export an x86 MP table
105 ## Useful for specifying IRQ routing values
107 default CONFIG_HAVE_MP_TABLE=1
110 ## Build code for SMP support
111 ## Only worry about 2 micro processors
114 default CONFIG_MAX_CPUS=4
115 default CONFIG_LOGICAL_CPUS=0
118 ## Build code to setup a generic IOAPIC
120 default CONFIG_IOAPIC=1
123 ## Clean up the motherboard id strings
125 default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon"
126 default CONFIG_MAINBOARD_VENDOR= "Intel"
127 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
128 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
131 ### Coreboot layout values
134 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
135 default CONFIG_ROM_IMAGE_SIZE = 65536
138 ## Use a small 8K stack
140 default CONFIG_STACK_SIZE=0x2000
143 ## Use a small 32K heap
145 default CONFIG_HEAP_SIZE=0x8000
149 ### Compute the location and size of where this firmware image
150 ### (coreboot plus bootloader) will live in the boot rom chip.
152 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
155 ## coreboot C code runs at this location in RAM
157 default CONFIG_RAMBASE=0x00004000
160 ## Load the payload from the ROM
162 default CONFIG_ROM_PAYLOAD=1
166 ### Defaults of options that you may want to override in the target config file
170 ## The default compiler
172 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
176 ## Disable the gdb stub by default
178 default CONFIG_GDB_STUB=0
181 ## The Serial Console
184 # To Enable the Serial Console
185 default CONFIG_CONSOLE_SERIAL8250=1
187 ## Select the serial console baud rate
188 default CONFIG_TTYS0_BAUD=115200
189 #default CONFIG_TTYS0_BAUD=57600
190 #default CONFIG_TTYS0_BAUD=38400
191 #default CONFIG_TTYS0_BAUD=19200
192 #default CONFIG_TTYS0_BAUD=9600
193 #default CONFIG_TTYS0_BAUD=4800
194 #default CONFIG_TTYS0_BAUD=2400
195 #default CONFIG_TTYS0_BAUD=1200
197 # Select the serial console base port
198 default CONFIG_TTYS0_BASE=0x3f8
200 # Select the serial protocol
201 # This defaults to 8 data bits, 1 stop bit, and no parity
202 default CONFIG_TTYS0_LCS=0x3
205 ### Select the coreboot loglevel
207 ## EMERG 1 system is unusable
208 ## ALERT 2 action must be taken immediately
209 ## CRIT 3 critical conditions
210 ## ERR 4 error conditions
211 ## WARNING 5 warning conditions
212 ## NOTICE 6 normal but significant condition
213 ## INFO 7 informational
214 ## CONFIG_DEBUG 8 debug-level messages
215 ## SPEW 9 way too many details
217 ## Request this level of debugging output
218 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
219 ## At a maximum only compile in this level of debugging
220 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
223 ## Select power on after power fail setting
224 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"