Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / intel / mtarvon / Kconfig
1 if BOARD_INTEL_MTARVON
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_INTEL_SOCKET_MPGA479M
7         select NORTHBRIDGE_INTEL_I3100
8         select SOUTHBRIDGE_INTEL_I3100
9         select SUPERIO_INTEL_I3100
10         select HAVE_HARD_RESET
11         select HAVE_PIRQ_TABLE
12         select HAVE_MP_TABLE
13         select UDELAY_TSC
14         select BOARD_ROMSIZE_KB_2048
15
16 config MAINBOARD_DIR
17         string
18         default intel/mtarvon
19
20 config MAINBOARD_PART_NUMBER
21         string
22         default "3100 devkit (Mt. Arvon)"
23
24 config IRQ_SLOT_COUNT
25         int
26         default 1
27
28 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
29         hex
30         default 0x8086
31
32 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
33         hex
34         default 0x2680
35
36 config DCACHE_RAM_BASE
37         hex
38         default 0xffdf8000
39
40 config DCACHE_RAM_SIZE
41         hex
42         default 0x8000
43
44 config MAX_CPUS
45         int
46         default 4
47
48 endif # BOARD_INTEL_MTARVON