2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
6 #include <cpu/x86/lapic.h>
8 #include "option_table.h"
9 #include "pc80/mc146818rtc_early.c"
10 #include "pc80/serial.c"
11 #include "console/console.c"
12 #include "lib/ramtest.c"
13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
14 #include "northbridge/intel/e7520/raminit.h"
15 #include "superio/nsc/pc87427/pc87427.h"
16 #include "cpu/x86/lapic/boot_cpu.c"
17 #include "cpu/x86/mtrr/earlymtrr.c"
20 #include "power_reset_check.c"
21 #include "jarrell_fixups.c"
22 #include "superio/nsc/pc87427/pc87427_early_init.c"
23 #include "northbridge/intel/e7520/memory_initialized.c"
24 #include "cpu/x86/bist.h"
26 #define SIO_GPIO_BASE 0x680
27 #define SIO_XBUS_BASE 0x4880
29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
30 #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
32 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
35 /* Beta values: 0x00090800 */
36 /* Silver values: 0x000a0900 */
37 #define RECVENA_CONFIG 0x000a090a
38 #define RECVENB_CONFIG 0x000a090a
39 #define DIMM_MAP_LOGICAL 0x0124
41 static inline int spd_read_byte(unsigned device, unsigned address)
43 return smbus_read_byte(device, address);
46 #include "northbridge/intel/e7520/raminit.c"
47 #include "lib/generic_sdram.c"
49 #include "arch/i386/lib/stages.c"
51 static void main(unsigned long bist)
57 static const struct mem_controller mch[] = {
61 .f0 = PCI_DEV(0, 0x00, 0),
62 .f1 = PCI_DEV(0, 0x00, 1),
63 .f2 = PCI_DEV(0, 0x00, 2),
64 .f3 = PCI_DEV(0, 0x00, 3),
66 .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
67 .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
72 /* Skip this if there was a built in self test failure */
74 if (memory_initialized()) {
78 /* Setup the console */
79 pc87427_disable_dev(CONSOLE_SERIAL_DEV);
80 pc87427_disable_dev(HIDDEN_SERIAL_DEV);
81 pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
82 /* Enable Serial 2 lines instead of GPIO */
84 outb((inb(0x2f) & (~1<<1)), 0x2f);
88 /* Halt if there was a built in self test failure */
89 report_bist_failure(bist);
91 pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
93 pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
94 xbus_cfg(PC87427_XBUS_DEV);
96 /* MOVE ME TO A BETTER LOCATION !!! */
97 /* config LPC decode for flash memory access */
99 dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
100 if (dev == PCI_DEV_INVALID) {
101 die("Missing ich5?");
103 pci_write_config32(dev, 0xe8, 0x00000000);
104 pci_write_config8(dev, 0xf0, 0x00);
111 // dump_spd_registers(&cpu[0]);
113 for(i = 0; i < 1; i++) {
114 dump_spd_registers();
118 power_down_reset_check();
119 // dump_ipmi_registers();
120 mainboard_set_e7520_leds();
121 sdram_initialize(ARRAY_SIZE(mch), mch);
127 dump_pci_device(PCI_DEV(0, 0x00, 0));
128 dump_bar14(PCI_DEV(0, 0x00, 0));
131 #if 0 // temporarily disabled
132 /* Check the first 1M */
133 // ram_check(0x00000000, 0x000100000);
134 // ram_check(0x00000000, 0x000a0000);
135 ram_check(0x00100000, 0x01000000);
136 /* check the first 1M in the 3rd Gig */
137 ram_check(0x30100000, 0x31000000);
139 ram_check(0x00000000, 0x02000000);