src/mainboard/intel/jarrell/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc87427/pc87427.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "watchdog.c"
  16 #include "reset.c"
  17 #include "power_reset_check.c"
  18 #include "jarrell_fixups.c"
  19 #include "superio/nsc/pc87427/pc87427_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22
  23 #define SIO_GPIO_BASE 0x680
  24 #define SIO_XBUS_BASE 0x4880
  25
  26 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  27 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  28
  29 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  30 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  31
  32 static inline int spd_read_byte(unsigned device, unsigned address)
  33 {
  34         return smbus_read_byte(device, address);
  35 }
  36
  37 #include "northbridge/intel/e7520/raminit.c"
  38 #include "lib/generic_sdram.c"
  39 #include "debug.c"
  40 #include "arch/i386/lib/stages.c"
  41
  42 static void main(unsigned long bist)
  43 {
  44         /*
  45          *
  46          *
  47          */
  48         static const struct mem_controller mch[] = {
  49                 {
  50                         .node_id = 0,
  51                         /*
  52                         .f0 = PCI_DEV(0, 0x00, 0),
  53                         .f1 = PCI_DEV(0, 0x00, 1),
  54                         .f2 = PCI_DEV(0, 0x00, 2),
  55                         .f3 = PCI_DEV(0, 0x00, 3),
  56                         */
  57                         .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
  58                         .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
  59                 }
  60         };
  61
  62         if (bist == 0) {
  63                 /* Skip this if there was a built in self test failure */
  64                 early_mtrr_init();
  65                 if (memory_initialized()) {
  66                         skip_romstage();
  67                 }
  68         }
  69         /* Setup the console */
  70         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  71         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  72         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  73         /* Enable Serial 2 lines instead of GPIO */
  74         outb(0x2c, 0x2e);
  75         outb((inb(0x2f) & (~1<<1)), 0x2f);
  76         uart_init();
  77         console_init();
  78
  79         /* Halt if there was a built in self test failure */
  80         report_bist_failure(bist);
  81
  82         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  83
  84         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  85         xbus_cfg(PC87427_XBUS_DEV);
  86
  87         /* MOVE ME TO A BETTER LOCATION !!! */
  88         /* config LPC decode for flash memory access */
  89         device_t dev;
  90         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  91         if (dev == PCI_DEV_INVALID) {
  92                 die("Missing ich5?");
  93         }
  94         pci_write_config32(dev, 0xe8, 0x00000000);
  95         pci_write_config8(dev, 0xf0, 0x00);
  96
  97 #if 0
  98         print_pci_devices();
  99 #endif
 100         enable_smbus();
 101 #if 0
 102 //      dump_spd_registers(&cpu[0]);
 103         int i;
 104         for(i = 0; i < 1; i++) {
 105                 dump_spd_registers();
 106         }
 107 #endif
 108         disable_watchdogs();
 109         power_down_reset_check();
 110 //      dump_ipmi_registers();
 111         mainboard_set_e7520_leds();
 112         sdram_initialize(ARRAY_SIZE(mch), mch);
 113         ich5_watchdog_on();
 114 #if 0
 115         dump_pci_devices();
 116 #endif
 117 #if 0
 118         dump_pci_device(PCI_DEV(0, 0x00, 0));
 119         dump_bar14(PCI_DEV(0, 0x00, 0));
 120 #endif
 121
 122 #if 0 // temporarily disabled
 123         /* Check the first 1M */
 124 //      ram_check(0x00000000, 0x000100000);
 125 //      ram_check(0x00000000, 0x000a0000);
 126         ram_check(0x00100000, 0x01000000);
 127         /* check the first 1M in the 3rd Gig */
 128         ram_check(0x30100000, 0x31000000);
 129 #if 0
 130         ram_check(0x00000000, 0x02000000);
 131 #endif
 132
 133 #endif
 134 #if 0
 135         while(1) {
 136                 hlt();
 137         }
 138 #endif
 139 }
 140