src/mainboard/intel/jarrell/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc87427/pc87427.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "watchdog.c"
  16 #include "reset.c"
  17 #include "power_reset_check.c"
  18 #include "jarrell_fixups.c"
  19 #include "superio/nsc/pc87427/pc87427_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define SIO_GPIO_BASE 0x680
  25 #define SIO_XBUS_BASE 0x4880
  26
  27 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  28 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  29
  30 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  31 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  32
  33 static inline int spd_read_byte(unsigned device, unsigned address)
  34 {
  35         return smbus_read_byte(device, address);
  36 }
  37
  38 #include "northbridge/intel/e7520/raminit.c"
  39 #include "lib/generic_sdram.c"
  40 #include "debug.c"
  41 #include "arch/i386/lib/stages.c"
  42
  43 static void main(unsigned long bist)
  44 {
  45         static const struct mem_controller mch[] = {
  46                 {
  47                         .node_id = 0,
  48                         /*
  49                         .f0 = PCI_DEV(0, 0x00, 0),
  50                         .f1 = PCI_DEV(0, 0x00, 1),
  51                         .f2 = PCI_DEV(0, 0x00, 2),
  52                         .f3 = PCI_DEV(0, 0x00, 3),
  53                         */
  54                         .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
  55                         .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
  56                 }
  57         };
  58
  59         if (bist == 0) {
  60                 /* Skip this if there was a built in self test failure */
  61                 early_mtrr_init();
  62                 if (memory_initialized()) {
  63                         skip_romstage();
  64                 }
  65         }
  66         /* Setup the console */
  67         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  68         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  69         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  70         /* Enable Serial 2 lines instead of GPIO */
  71         outb(0x2c, 0x2e);
  72         outb((inb(0x2f) & (~1<<1)), 0x2f);
  73         uart_init();
  74         console_init();
  75
  76         /* Halt if there was a built in self test failure */
  77         report_bist_failure(bist);
  78
  79         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  80
  81         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  82         xbus_cfg(PC87427_XBUS_DEV);
  83
  84         /* MOVE ME TO A BETTER LOCATION !!! */
  85         /* config LPC decode for flash memory access */
  86         device_t dev;
  87         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  88         if (dev == PCI_DEV_INVALID) {
  89                 die("Missing ich5?");
  90         }
  91         pci_write_config32(dev, 0xe8, 0x00000000);
  92         pci_write_config8(dev, 0xf0, 0x00);
  93
  94 #if 0
  95         print_pci_devices();
  96 #endif
  97         enable_smbus();
  98 #if 0
  99 //      dump_spd_registers(&cpu[0]);
 100         int i;
 101         for(i = 0; i < 1; i++) {
 102                 dump_spd_registers();
 103         }
 104 #endif
 105         disable_watchdogs();
 106         power_down_reset_check();
 107 //      dump_ipmi_registers();
 108         mainboard_set_e7520_leds();
 109         sdram_initialize(ARRAY_SIZE(mch), mch);
 110         ich5_watchdog_on();
 111 #if 0
 112         dump_pci_devices();
 113 #endif
 114 #if 0
 115         dump_pci_device(PCI_DEV(0, 0x00, 0));
 116         dump_bar14(PCI_DEV(0, 0x00, 0));
 117 #endif
 118
 119 #if 0 // temporarily disabled
 120         /* Check the first 1M */
 121 //      ram_check(0x00000000, 0x000100000);
 122 //      ram_check(0x00000000, 0x000a0000);
 123         ram_check(0x00100000, 0x01000000);
 124         /* check the first 1M in the 3rd Gig */
 125         ram_check(0x30100000, 0x31000000);
 126 #if 0
 127         ram_check(0x00000000, 0x02000000);
 128 #endif
 129
 130 #endif
 131 #if 0
 132         while(1) {
 133                 hlt();
 134         }
 135 #endif
 136 }
 137