1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 struct mp_config_table *mc;
12 unsigned char bus_pxhd_1;
13 unsigned char bus_pxhd_2;
14 unsigned char bus_pxhd_3 = 0;
15 unsigned char bus_pxhd_4 = 0;
16 unsigned char bus_pxhd_x = 0;
17 unsigned char bus_ich5r_1;
18 unsigned int bus_pxhd_id;
20 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
22 mptable_init(mc, LAPIC_ADDR);
24 smp_write_processors(mc);
30 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
32 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
35 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
40 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
42 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
46 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
51 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
53 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
57 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
61 /* test for active riser with 2nd pxh device */
62 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
64 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
65 if(bus_pxhd_id == 0x35998086) {
66 bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
68 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
70 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
71 if(bus_pxhd_id == 0x03298086) {
72 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
76 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
78 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
79 if(bus_pxhd_id == 0x032a8086) {
80 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
87 mptable_write_buses(mc, NULL, &bus_isa);
91 smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
96 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
98 res = find_resource(dev, PCI_BASE_ADDRESS_0);
100 smp_write_ioapic(mc, 0x09, 0x20, res->base);
104 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
107 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
109 res = find_resource(dev, PCI_BASE_ADDRESS_0);
111 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
115 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
119 if(bus_pxhd_3) { /* Active riser pxhd */
120 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
122 res = find_resource(dev, PCI_BASE_ADDRESS_0);
124 smp_write_ioapic(mc, 0x0b, 0x20, res->base);
128 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
132 if(bus_pxhd_4) { /* active riser pxhd */
133 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
135 res = find_resource(dev, PCI_BASE_ADDRESS_0);
137 smp_write_ioapic(mc, 0x0c, 0x20, res->base);
141 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
146 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
149 bus_isa, 0x0a, 0x08, 0x10);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
151 bus_isa, 0x0b, 0x08, 0x11);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
153 bus_isa, 0x0a, 0x08, 0x10);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
155 bus_isa, 0x07, 0x08, 0x13);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
157 bus_isa, 0x0b, 0x08, 0x12);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
159 bus_isa, 0x05, 0x08, 0x17);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
161 bus_isa, 0x0b, 0x08, 0x12);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
163 bus_isa, 0x07, 0x08, 0x13);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
165 bus_isa, 0x0b, 0x08, 0x11);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
167 bus_isa, 0x0a, 0x08, 0x10);
169 /* Standard local interrupt assignments */
170 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
171 bus_isa, 0x00, MP_APIC_ALL, 0x00);
172 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_isa, 0x00, MP_APIC_ALL, 0x01);
175 /* FIXME verify I have the irqs handled for all of the risers */
177 /* 2:3.0 PCI Slot 1 */
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
179 bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
181 bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
183 bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
185 bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
188 /* 3:7.0 PCI Slot 2 */
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
190 bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
192 bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
194 bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
196 bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
198 /* PCI Slot 3 (if active riser) */
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
201 bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
204 /* PCI Slot 4 (if active riser) */
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
207 bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
212 bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
215 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
216 bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
219 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
220 bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
223 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
224 bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
227 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
228 bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
230 /* There is no extension information... */
232 /* Compute the checksums */
233 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
235 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
236 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
237 mc, smp_next_mpe_entry(mc));
238 return smp_next_mpe_entry(mc);
241 unsigned long write_smp_table(unsigned long addr)
244 v = smp_write_floating_table(addr);
245 return (unsigned long)smp_write_config_table(v);