1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "SE7520JR20 ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_pxhd_1;
16 unsigned char bus_pxhd_2;
17 unsigned char bus_pxhd_3 = 0;
18 unsigned char bus_pxhd_4 = 0;
19 unsigned char bus_pxhd_x = 0;
20 unsigned char bus_ich5r_1;
21 unsigned int bus_pxhd_id;
23 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
24 memset(mc, 0, sizeof(*mc));
26 memcpy(mc->mpc_signature, sig, sizeof(sig));
27 mc->mpc_length = sizeof(*mc); /* initially just the header */
29 mc->mpc_checksum = 0; /* not yet computed */
30 memcpy(mc->mpc_oem, oem, sizeof(oem));
31 memcpy(mc->mpc_productid, productid, sizeof(productid));
34 mc->mpc_entry_count = 0; /* No entries yet... */
35 mc->mpc_lapic = LAPIC_ADDR;
40 smp_write_processors(mc);
46 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
48 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
49 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
53 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
59 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
61 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
65 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
70 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
72 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
76 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
80 /* test for active riser with 2nd pxh device */
81 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
83 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
84 if(bus_pxhd_id == 0x35998086) {
85 bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
87 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
89 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
90 if(bus_pxhd_id == 0x03298086) {
91 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
95 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
97 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
98 if(bus_pxhd_id == 0x032a8086) {
99 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
106 /* define bus and isa numbers */
107 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
108 smp_write_bus(mc, bus_num, "PCI ");
110 smp_write_bus(mc, bus_isa, "ISA ");
112 /* IOAPIC handling */
114 smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
116 struct resource *res;
119 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
121 res = find_resource(dev, PCI_BASE_ADDRESS_0);
123 smp_write_ioapic(mc, 0x09, 0x20, res->base);
127 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
130 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
132 res = find_resource(dev, PCI_BASE_ADDRESS_0);
134 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
138 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
142 if(bus_pxhd_3) { /* Active riser pxhd */
143 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
145 res = find_resource(dev, PCI_BASE_ADDRESS_0);
147 smp_write_ioapic(mc, 0x0b, 0x20, res->base);
151 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
155 if(bus_pxhd_4) { /* active riser pxhd */
156 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
158 res = find_resource(dev, PCI_BASE_ADDRESS_0);
160 smp_write_ioapic(mc, 0x0c, 0x20, res->base);
164 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
169 /* ISA backward compatibility interrupts */
170 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
171 bus_isa, 0x00, 0x08, 0x00);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_isa, 0x01, 0x08, 0x01);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
175 bus_isa, 0x00, 0x08, 0x02);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
177 bus_isa, 0x03, 0x08, 0x03);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
179 bus_isa, 0x04, 0x08, 0x04);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
181 bus_isa, 0x06, 0x08, 0x06);
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
183 bus_isa, 0x08, 0x08, 0x08);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
185 bus_isa, 0x09, 0x08, 0x09);
186 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
187 bus_isa, 0x0c, 0x08, 0x0c);
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
189 bus_isa, 0x0d, 0x08, 0x0d);
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
191 bus_isa, 0x0e, 0x08, 0x0e);
192 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
193 bus_isa, 0x0f, 0x08, 0x0f);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
195 bus_isa, 0x0a, 0x08, 0x10);
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
197 bus_isa, 0x0b, 0x08, 0x11);
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
199 bus_isa, 0x0a, 0x08, 0x10);
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
201 bus_isa, 0x07, 0x08, 0x13);
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
203 bus_isa, 0x0b, 0x08, 0x12);
204 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
205 bus_isa, 0x05, 0x08, 0x17);
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
207 bus_isa, 0x0b, 0x08, 0x12);
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
209 bus_isa, 0x07, 0x08, 0x13);
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
211 bus_isa, 0x0b, 0x08, 0x11);
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
213 bus_isa, 0x0a, 0x08, 0x10);
215 /* Standard local interrupt assignments */
216 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
217 bus_isa, 0x00, MP_APIC_ALL, 0x00);
218 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
219 bus_isa, 0x00, MP_APIC_ALL, 0x01);
221 /* FIXME verify I have the irqs handled for all of the risers */
223 /* 2:3.0 PCI Slot 1 */
224 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
225 bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
226 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
227 bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
228 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
229 bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
230 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
231 bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
234 /* 3:7.0 PCI Slot 2 */
235 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
236 bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
237 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
238 bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
239 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
240 bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
241 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
242 bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
244 /* PCI Slot 3 (if active riser) */
246 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
247 bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
250 /* PCI Slot 4 (if active riser) */
252 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
253 bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
257 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
258 bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
261 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
262 bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
265 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
266 bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
269 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
270 bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
273 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
274 bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
276 /* There is no extension information... */
278 /* Compute the checksums */
279 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
281 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
282 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
283 mc, smp_next_mpe_entry(mc));
284 return smp_next_mpe_entry(mc);
287 unsigned long write_smp_table(unsigned long addr)
290 v = smp_write_floating_table(addr);
291 return (unsigned long)smp_write_config_table(v);