src/mainboard/intel/jarrell/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         struct mp_config_table *mc;
  11         int bus_isa;
  12         unsigned char bus_pxhd_1;
  13         unsigned char bus_pxhd_2;
  14         unsigned char bus_pxhd_3 = 0;
  15         unsigned char bus_pxhd_4 = 0;
  16         unsigned char bus_pxhd_x = 0;
  17         unsigned char bus_ich5r_1;
  18         unsigned int bus_pxhd_id;
  19
  20         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  21
  22         mptable_init(mc, LOCAL_APIC_ADDR);
  23
  24         smp_write_processors(mc);
  25
  26         {
  27                 device_t dev;
  28
  29                 /* ich5r */
  30                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  31                 if (dev) {
  32                         bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  33                 }
  34                 else {
  35                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
  36
  37                         bus_ich5r_1 = 4;
  38                 }
  39                 /* pxhd-1 */
  40                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  41                 if (dev) {
  42                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  43
  44                 }
  45                 else {
  46                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  47
  48                         bus_pxhd_1 = 2;
  49                 }
  50                 /* pxhd-2 */
  51                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  52                 if (dev) {
  53                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  54
  55                 }
  56                 else {
  57                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  58
  59                         bus_pxhd_2 = 3;
  60                 }
  61                 /* test for active riser with 2nd pxh device */
  62                 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
  63                 if (dev) {
  64                         bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
  65                         if(bus_pxhd_id == 0x35998086) {
  66                                 bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
  67                                 /* pxhd-3 */
  68                                 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
  69                                 if (dev) {
  70                                         bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
  71                                         if(bus_pxhd_id == 0x03298086) {
  72                                             bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  73                                         }
  74                                 }
  75                                 /* pxhd-4 */
  76                                 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
  77                                 if (dev) {
  78                                         bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
  79                                         if(bus_pxhd_id == 0x032a8086) {
  80                                             bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  81                                         }
  82                                 }
  83                         }
  84                 }
  85         }
  86
  87         mptable_write_buses(mc, NULL, &bus_isa);
  88
  89         /* IOAPIC handling */
  90
  91         smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
  92         {
  93                 struct resource *res;
  94                 device_t dev;
  95                 /* pxhd apic 3 */
  96                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  97                 if (dev) {
  98                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  99                         if (res) {
 100                                 smp_write_ioapic(mc, 0x09, 0x20, res->base);
 101                         }
 102                 }
 103                 else {
 104                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 105                 }
 106                 /* pxhd apic 4 */
 107                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 108                 if (dev) {
 109                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 110                         if (res) {
 111                                 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
 112                         }
 113                 }
 114                 else {
 115                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 116                 }
 117
 118                 /* pxhd apic 5 */
 119                 if(bus_pxhd_3) { /* Active riser pxhd */
 120                         dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
 121                         if (dev) {
 122                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 123                                 if (res) {
 124                                         smp_write_ioapic(mc, 0x0b, 0x20, res->base);
 125                                 }
 126                         }
 127                         else {
 128                                 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
 129                         }
 130                 }
 131                 /* pxhd apic 6 */
 132                 if(bus_pxhd_4) { /* active riser pxhd */
 133                         dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
 134                         if (dev) {
 135                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 136                                 if (res) {
 137                                         smp_write_ioapic(mc, 0x0c, 0x20, res->base);
 138                                 }
 139                         }
 140                         else {
 141                                 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
 142                         }
 143                 }
 144         }
 145
 146         mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
 147
 148         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 149                 bus_isa, 0x0a, 0x08, 0x10);
 150         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 151                 bus_isa, 0x0b, 0x08, 0x11);
 152         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 153                 bus_isa, 0x0a, 0x08, 0x10);
 154         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 155                 bus_isa, 0x07, 0x08, 0x13);
 156         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 157                 bus_isa, 0x0b, 0x08, 0x12);
 158         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 159                 bus_isa, 0x05, 0x08, 0x17);
 160         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 161                 bus_isa, 0x0b, 0x08, 0x12);
 162         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 163                 bus_isa, 0x07, 0x08, 0x13);
 164         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 165                 bus_isa, 0x0b, 0x08, 0x11);
 166         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 167                 bus_isa, 0x0a, 0x08, 0x10);
 168
 169         /* Standard local interrupt assignments */
 170         mptable_lintsrc(mc, bus_isa);
 171
 172         /* FIXME verify I have the irqs handled for all of the risers */
 173
 174         /* 2:3.0 PCI Slot 1 */
 175         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 176                 bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
 177         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 178                 bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
 179         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 180                 bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
 181         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 182                 bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
 183
 184
 185         /* 3:7.0 PCI Slot 2 */
 186         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 187                 bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
 188         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 189                 bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
 190         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 191                 bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
 192         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 193                 bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
 194
 195         /* PCI Slot 3 (if active riser) */
 196         if(bus_pxhd_3) {
 197                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 198                         bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
 199         }
 200
 201         /* PCI Slot 4 (if active riser) */
 202         if(bus_pxhd_4) {
 203                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 204                         bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
 205         }
 206
 207         /* Onboard SCSI 0 */
 208         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 209                 bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
 210
 211         /* Onboard SCSI 1 */
 212         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 213                 bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
 214
 215         /* Onboard NIC 0 */
 216         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 217                 bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
 218
 219         /* Onboard NIC 1 */
 220         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 221                 bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
 222
 223         /* Onboard VGA */
 224         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 225                  bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
 226
 227         /* There is no extension information... */
 228
 229         /* Compute the checksums */
 230         return mptable_finalize(mc);
 231 }
 232
 233 unsigned long write_smp_table(unsigned long addr)
 234 {
 235         void *v;
 236         v = smp_write_floating_table(addr, 0);
 237         return (unsigned long)smp_write_config_table(v);
 238 }
 239