1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
8 uses CONFIG_LOGICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
20 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_XIP_ROM_SIZE
23 uses CONFIG_XIP_ROM_BASE
24 uses CONFIG_STACK_SIZE
26 uses CONFIG_USE_OPTION_TABLE
27 uses CONFIG_LB_CKS_RANGE_START
28 uses CONFIG_LB_CKS_RANGE_END
29 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_MAINBOARD_PART_NUMBER
32 uses CONFIG_MAINBOARD_VENDOR
33 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
35 uses COREBOOT_EXTRA_VERSION
36 uses CONFIG_UDELAY_TSC
37 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
40 uses CONFIG_CONSOLE_SERIAL8250
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_BTEXT
50 uses CONFIG_CROSS_COMPILE
52 uses CONFIG_MAX_REBOOT_CNT
53 uses CONFIG_USE_WATCHDOG_ON_BOOT
61 ## Because we do the stutter start we need more attempts
63 default CONFIG_MAX_REBOOT_CNT=8
66 ## Use the watchdog to break out of a lockup condition
68 default CONFIG_USE_WATCHDOG_ON_BOOT=1
71 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
73 default CONFIG_ROM_SIZE=2097152
77 ## Build code for the fallback boot
79 default CONFIG_HAVE_FALLBACK_BOOT=1
82 ## Delay timer options
85 default CONFIG_UDELAY_TSC=1
86 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
89 ## Build code to reset the motherboard from coreboot
91 default CONFIG_HAVE_HARD_RESET=1
94 ## Build code to export a programmable irq routing table
96 default CONFIG_HAVE_PIRQ_TABLE=1
97 default CONFIG_IRQ_SLOT_COUNT=18
100 ## Build code to export an x86 MP table
101 ## Useful for specifying IRQ routing values
103 default CONFIG_HAVE_MP_TABLE=1
106 ## Build code to export a CMOS option table
108 default CONFIG_HAVE_OPTION_TABLE=1
111 ## Move the default coreboot cmos range off of AMD RTC registers
113 default CONFIG_LB_CKS_RANGE_START=49
114 default CONFIG_LB_CKS_RANGE_END=122
115 default CONFIG_LB_CKS_LOC=123
118 ## Build code for SMP support
119 ## Only worry about 2 micro processors
122 default CONFIG_MAX_CPUS=4
123 default CONFIG_LOGICAL_CPUS=0
126 ## Build code to setup a generic IOAPIC
128 default CONFIG_IOAPIC=1
131 ## Clean up the motherboard id strings
133 default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
134 default CONFIG_MAINBOARD_VENDOR= "Intel"
135 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
136 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
137 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
140 ### coreboot layout values
143 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
144 default CONFIG_ROM_IMAGE_SIZE = 65536
147 ## Use a small 8K stack
149 default CONFIG_STACK_SIZE=0x2000
152 ## Use a small 32K heap
154 default CONFIG_HEAP_SIZE=0x8000
158 ### Compute the location and size of where this firmware image
159 ### (coreboot plus bootloader) will live in the boot rom chip.
161 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
164 ## Coreboot C code runs at this location in RAM
166 default CONFIG_RAMBASE=0x00004000
169 ## Load the payload from the ROM
171 default CONFIG_ROM_PAYLOAD=1
175 ### Defaults of options that you may want to override in the target config file
179 ## The default compiler
181 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
185 ## Disable the gdb stub by default
187 default CONFIG_GDB_STUB=0
190 ## The Serial Console
193 # To Enable the Serial Console
194 default CONFIG_CONSOLE_SERIAL8250=1
196 ## Select the serial console baud rate
197 default CONFIG_TTYS0_BAUD=115200
198 #default CONFIG_TTYS0_BAUD=57600
199 #default CONFIG_TTYS0_BAUD=38400
200 #default CONFIG_TTYS0_BAUD=19200
201 #default CONFIG_TTYS0_BAUD=9600
202 #default CONFIG_TTYS0_BAUD=4800
203 #default CONFIG_TTYS0_BAUD=2400
204 #default CONFIG_TTYS0_BAUD=1200
206 # Select the serial console base port
207 default CONFIG_TTYS0_BASE=0x3f8
209 # Select the serial protocol
210 # This defaults to 8 data bits, 1 stop bit, and no parity
211 default CONFIG_TTYS0_LCS=0x3
214 ### Select the coreboot loglevel
216 ## EMERG 1 system is unusable
217 ## ALERT 2 action must be taken immediately
218 ## CRIT 3 critical conditions
219 ## ERR 4 error conditions
220 ## WARNING 5 warning conditions
221 ## NOTICE 6 normal but significant condition
222 ## INFO 7 informational
223 ## CONFIG_DEBUG 8 debug-level messages
224 ## SPEW 9 Way too many details
226 ## Request this level of debugging output
227 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
228 ## At a maximum only compile in this level of debugging
229 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
232 ## Select power on after power fail setting
233 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
236 ## Don't enable the btext console
238 default CONFIG_CONSOLE_BTEXT=0