2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
27 #include <arch/romcc_io.h>
28 #include <device/pci_def.h>
29 #include <device/pnp_def.h>
30 #include <cpu/x86/lapic.h>
32 #include <pc80/mc146818rtc.h>
34 #include <console/console.h>
35 #include <cpu/x86/bist.h>
37 #include "southbridge/intel/i3100/i3100_early_smbus.c"
38 #include "southbridge/intel/i3100/i3100_early_lpc.c"
40 #include "superio/intel/i3100/i3100_early_serial.c"
41 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
43 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
44 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
46 #define IA32_PERF_STS 0x198
47 #define IA32_PERF_CTL 0x199
48 #define MSR_THERM2_CTL 0x19D
49 #define IA32_MISC_ENABLES 0x1A0
54 #define SATA_MODE_IDE 0x00
55 #define SATA_MODE_AHCI 0x01
59 #define DEFAULT_RCBA 0xFEA00000
61 #define RCBA_RPC 0x0224 /* 32 bit */
63 #define RCBA_TCTL 0x3000 /* 8 bit */
65 #define RCBA_D31IP 0x3100 /* 32 bit */
66 #define RCBA_D30IP 0x3104 /* 32 bit */
67 #define RCBA_D29IP 0x3108 /* 32 bit */
68 #define RCBA_D28IP 0x310C /* 32 bit */
69 #define RCBA_D31IR 0x3140 /* 16 bit */
70 #define RCBA_D30IR 0x3142 /* 16 bit */
71 #define RCBA_D29IR 0x3144 /* 16 bit */
72 #define RCBA_D28IR 0x3146 /* 16 bit */
74 #define RCBA_RTC 0x3400 /* 32 bit */
75 #define RCBA_HPTC 0x3404 /* 32 bit */
76 #define RCBA_GCS 0x3410 /* 32 bit */
77 #define RCBA_BUC 0x3414 /* 8 bit */
78 #define RCBA_FD 0x3418 /* 32 bit */
79 #define RCBA_PRC 0x341C /* 32 bit */
81 static inline int spd_read_byte(u16 device, u8 address)
83 return smbus_read_byte(device, address);
86 #include "northbridge/intel/i3100/raminit.h"
87 #include "cpu/x86/mtrr/earlymtrr.c"
88 #include "northbridge/intel/i3100/memory_initialized.c"
89 #include "northbridge/intel/i3100/raminit.c"
90 #include "lib/generic_sdram.c"
91 #include "northbridge/intel/i3100/reset_test.c"
94 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
96 static void early_config(void)
101 pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
103 /* Disable watchdog */
104 gcs = read32(DEFAULT_RCBA + RCBA_GCS);
105 gcs |= (1 << 5); /* No reset */
106 write32(DEFAULT_RCBA + RCBA_GCS, gcs);
108 /* Configure PCIe port B as 4x */
109 rpc = read32(DEFAULT_RCBA + RCBA_RPC);
111 write32(DEFAULT_RCBA + RCBA_RPC, rpc);
113 /* Disable Modem, Audio, PCIe ports 2/3/4 */
114 fd = read32(DEFAULT_RCBA + RCBA_FD);
115 fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
116 write32(DEFAULT_RCBA + RCBA_FD, fd);
119 write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
121 /* Improve interrupt routing
122 * D31:F2 SATA INTB# -> PIRQD
123 * D31:F3 SMBUS INTB# -> PIRQD
124 * D31:F4 CHAP INTD# -> PIRQA
125 * D29:F0 USB1#1 INTA# -> PIRQH
126 * D29:F1 USB1#2 INTB# -> PIRQD
127 * D29:F7 USB2 INTA# -> PIRQH
128 * D28:F0 PCIe Port 1 INTA# -> PIRQE
131 write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
132 write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
133 write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
134 write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
136 /* Setup sata mode */
137 pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
140 void main(unsigned long bist)
142 /* int boot_mode = 0; */
144 static const struct mem_controller mch[] = {
147 .f0 = PCI_DEV(0, 0x00, 0),
148 .f1 = PCI_DEV(0, 0x00, 1),
149 .f2 = PCI_DEV(0, 0x00, 2),
150 .f3 = PCI_DEV(0, 0x00, 3),
151 .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
152 .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
160 /* Setup the console */
161 i3100_enable_superio();
162 i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
163 i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
168 /* Halt if there was a built in self test failure */
169 report_bist_failure(bist);
171 /* Perform early board specific init */
174 /* Prevent the TCO timer from rebooting us */
175 i3100_halt_tco_timer();
177 /* Enable SPD ROMs and DDR-II DRAM */
180 /* Enable SpeedStep and automatic thermal throttling */
185 msr = rdmsr(IA32_MISC_ENABLES);
186 msr.lo |= (1 << 3) | (1 << 16);
187 wrmsr(IA32_MISC_ENABLES, msr);
189 /* Set CPU frequency/voltage to maximum */
191 /* Read performance status register and keep
192 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
195 msr = rdmsr(IA32_PERF_STS);
196 perf = msr.hi & 0x0000ffff;
198 /* Write VID_MAX & BUS_RATIO_MAX to
199 * performance control register
201 msr = rdmsr(IA32_PERF_CTL);
202 msr.lo &= 0xffff0000;
204 wrmsr(IA32_PERF_CTL, msr);
207 /* Initialize memory */
208 sdram_initialize(ARRAY_SIZE(mch), mch);