2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <console/console.h>
25 #include <arch/ioapic.h>
26 #include <arch/smp/mpspec.h>
27 #include <device/pci.h>
31 // Generate MP-table IRQ numbers for PCI devices.
38 #define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
52 #define RCBA_D31IP 0x3100
53 #define RCBA_D30IP 0x3104
54 #define RCBA_D29IP 0x3108
55 #define RCBA_D28IP 0x310C
56 #define RCBA_D31IR 0x3140
57 #define RCBA_D30IR 0x3142
58 #define RCBA_D29IR 0x3144
59 #define RCBA_D28IR 0x3146
61 static void *smp_write_config_table(void *v)
63 struct mp_config_table *mc;
64 unsigned char bus_chipset, bus_pci;
65 unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
72 dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
73 res = find_resource(dev, RCBA);
79 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
81 mptable_init(mc, "EagleHeights", LAPIC_ADDR);
83 smp_write_processors(mc);
89 dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
91 bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
93 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
97 dev = dev_find_slot(0, PCI_DEVFN(2,0));
99 bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
101 printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A 0:2.0, using defaults\n");
105 dev = dev_find_slot(0, PCI_DEVFN(3,0));
107 bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
109 printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
113 dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
115 bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
117 printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
121 mptable_write_buses(mc, NULL, &bus_isa);
123 /*I/O APICs: APIC ID Version State Address*/
124 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
126 mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
128 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
129 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
130 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
132 /* Internal PCI device for i3100 */
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
148 for(i = 0; i < 4; i++) {
149 pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
152 route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
157 /* USB 1.1 : device 29, function 0, 1
159 for(i = 0; i < 2; i++) {
160 pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
163 route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
168 /* USB 2.0 : device 29, function 7
170 pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
173 route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
177 /* SATA : device 31 function 2
178 SMBus : device 31 function 3
179 Performance counters : device 31 function 4
181 for(i = 2; i < 5; i++) {
182 pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
185 route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
186 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
204 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
215 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
216 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
217 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
218 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
220 /* There is no extension information... */
222 /* Compute the checksums */
223 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
224 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
225 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
226 mc, smp_next_mpe_entry(mc));
227 return smp_next_mpe_entry(mc);
230 unsigned long write_smp_table(unsigned long addr)
233 v = smp_write_floating_table(addr);
234 return (unsigned long)smp_write_config_table(v);