2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 ## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
27 ## Only use the option table in a normal image
29 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
31 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
32 default CONFIG_XIP_ROM_SIZE = 64 * 1024
33 include /config/nofailovercalculation.lb
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if CONFIG_GENERATE_MP_TABLE object mptable.o end
47 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
49 if CONFIG_GENERATE_ACPI_TABLES
53 depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
54 action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
55 action "mv $(CURDIR)/dsdt.hex dsdt.c"
65 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
66 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
72 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
73 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
74 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
75 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
81 ## Build our 16 bit and 32 bit coreboot entry code
83 mainboardinit cpu/x86/16bit/entry16.inc
84 mainboardinit cpu/x86/32bit/entry32.inc
85 ldscript /cpu/x86/16bit/entry16.lds
87 ldscript /cpu/x86/32bit/entry32.lds
88 ldscript /cpu/x86/car/cache_as_ram.lds
92 ## Build our reset vector (This is where coreboot is entered)
94 if CONFIG_USE_FALLBACK_IMAGE
95 mainboardinit cpu/x86/16bit/reset16.inc
96 ldscript /cpu/x86/16bit/reset16.lds
98 mainboardinit cpu/x86/32bit/reset32.inc
99 ldscript /cpu/x86/32bit/reset32.lds
104 ## Include an id string (For safe flashing)
106 mainboardinit arch/i386/lib/id.inc
107 ldscript /arch/i386/lib/id.lds
110 ## Setup Cache-As-Ram
112 mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
115 ### This is the early phase of coreboot startup
116 ### Things are delicate and we test to see if we should
117 ### failover to another image.
119 if CONFIG_USE_FALLBACK_IMAGE
120 ldscript /arch/i386/lib/failover.lds
124 ### O.k. We aren't just an intermediary anymore!
130 mainboardinit ./auto.inc
134 ## Include the secondary Configuration files
139 chip northbridge/intel/i3100
140 device pci_domain 0 on
141 device pci 00.0 on end # IMCH
142 device pci 00.1 on end # IMCH error status
143 device pci 01.0 on end # IMCH EDMA engine
144 device pci 02.0 on end # PCIe port A/A0
145 device pci 03.0 on end # PCIe port A1
146 chip southbridge/intel/i3100
147 # PIRQ line -> legacy IRQ mappings
148 register "pirq_a_d" = "0x8b808a8a"
149 register "pirq_e_h" = "0x85808080"
151 device pci 1c.0 on end # PCIe port B0
152 device pci 1c.1 off end # PCIe port B1
153 device pci 1c.2 off end # PCIe port B2
154 device pci 1c.3 off end # PCIe port B3
155 device pci 1d.0 on end # USB (UHCI) 1
156 device pci 1d.1 on end # USB (UHCI) 2
157 device pci 1d.7 on end # USB (EHCI)
158 device pci 1e.0 on end # PCI bridge
159 device pci 1f.0 on # LPC bridge
160 chip superio/intel/i3100
161 device pnp 4e.4 on # Com1
165 device pnp 4e.5 on # Com2
170 chip superio/smsc/smscsuperio
171 device pnp 2e.0 off # Floppy
176 device pnp 2e.2 off # Serial Port 4
180 device pnp 2e.3 on # Parallel Port
185 device pnp 2e.4 off # Serial Port 3
189 device pnp 2e.7 on # PS/2 Keyboard / Mouse
192 irq 0x70 = 1 # PS/2 keyboard interrupt
193 irq 0x72 = 12 # PS/2 mouse interrupt
195 device pnp 2e.a off # Runtime registers
200 device pci 1f.2 on end # SATA
201 device pci 1f.3 on end # SMBus
202 device pci 1f.4 on end # Performance counters
205 device apic_cluster 0 on
206 chip cpu/intel/bga956