2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
22 /* Configuration of the i945 driver */
23 #define CHIPSET_I945GC 1
24 #define CHANNEL_XOR_RANDOMIZATION 1
29 #include <arch/romcc_io.h>
30 #include <device/pci_def.h>
31 #include <device/pnp_def.h>
32 #include <cpu/x86/lapic.h>
34 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
36 #include "option_table.h"
37 #include "pc80/mc146818rtc_early.c"
39 #include <console/console.h>
40 #include <cpu/x86/bist.h>
42 #if CONFIG_USBDEBUG_DIRECT
43 #define DBGP_DEFAULT 1
44 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
45 #include "pc80/usbdebug_serial.c"
48 #include "lib/ramtest.c"
49 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
50 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
52 #include "northbridge/intel/i945/udelay.c"
54 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
56 #include "southbridge/intel/i82801gx/i82801gx.h"
57 static void setup_ich7_gpios(void)
59 /* TODO: This is highly board specific and should be moved */
60 printk(BIOS_DEBUG, " GPIOS...");
61 /* General Registers */
62 outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
63 outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
64 outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
65 /* Output Control Registers */
66 outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
67 /* Input Control Registers */
68 outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
69 outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
70 outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
71 outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
74 #include "northbridge/intel/i945/early_init.c"
76 static inline int spd_read_byte(unsigned device, unsigned address)
78 return smbus_read_byte(device, address);
81 #include "northbridge/intel/i945/raminit.h"
82 #include "northbridge/intel/i945/raminit.c"
83 #include "northbridge/intel/i945/errata.c"
84 #include "northbridge/intel/i945/debug.c"
86 static void ich7_enable_lpc(void)
89 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
90 // Set COM1/COM2 decode range
91 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
93 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
94 // Enable SuperIO Power Management Events
95 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
98 /* This box has two superios, so enabling serial becomes slightly excessive.
99 * We disable a lot of stuff to make sure that there are no conflicts between
100 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
101 * but safe anyways" method.
103 static void early_superio_config_lpc47m15x(void)
107 dev=PNP_DEV(0x2e, LPC47M15X_SP1);
108 pnp_enter_conf_state(dev);
110 pnp_set_logical_device(dev);
111 pnp_set_enable(dev, 0);
112 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
113 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
114 pnp_set_enable(dev, 1);
116 /* Enable SuperIO PM */
117 dev=PNP_DEV(0x2e, LPC47M15X_PME);
118 pnp_set_logical_device(dev);
119 pnp_set_enable(dev, 0);
120 pnp_set_iobase(dev, PNP_IDX_IO0, 0x680);
121 pnp_set_enable(dev, 1);
123 pnp_exit_conf_state(dev);
126 static void rcba_config(void)
128 /* Set up virtual channel 0 */
129 //RCBA32(0x0014) = 0x80000001;
130 //RCBA32(0x001c) = 0x03128010;
132 /* Device 1f interrupt pin register */
133 RCBA32(0x3100) = 0x00042210;
134 /* Device 1d interrupt pin register */
135 RCBA32(0x310c) = 0x00214321;
137 /* dev irq route register */
138 RCBA16(0x3140) = 0x0132;
139 RCBA16(0x3142) = 0x0146;
140 RCBA16(0x3144) = 0x0237;
141 RCBA16(0x3146) = 0x3201;
142 RCBA16(0x3148) = 0x0146;
145 RCBA8(0x31ff) = 0x03;
147 /* Enable upper 128bytes of CMOS */
148 RCBA32(0x3400) = (1 << 2);
150 /* Disable unused devices */
151 //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
152 // RCBA32(0x3418) |= (1 << 0); // Required.
154 RCBA32(0x3418) = 0x003204e1;
156 /* Enable PCIe Root Port Clock Gate */
157 // RCBA32(0x341c) = 0x00000001;
160 static void early_ich7_init(void)
165 // program secondary mlt XXX byte?
166 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
168 // reset rtc power status
169 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
171 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
173 // usb transient disconnect
174 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
176 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
178 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
179 reg32 |= (1 << 29) | (1 << 17);
180 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
182 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
183 reg32 |= (1 << 31) | (1 << 27);
184 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
186 RCBA32(0x0088) = 0x0011d000;
187 RCBA16(0x01fc) = 0x060f;
188 RCBA32(0x01f4) = 0x86000040;
189 RCBA32(0x0214) = 0x10030549;
190 RCBA32(0x0218) = 0x00020504;
191 RCBA8(0x0220) = 0xc5;
192 reg32 = RCBA32(0x3410);
194 RCBA32(0x3410) = reg32;
195 reg32 = RCBA32(0x3430);
198 RCBA32(0x3430) = reg32;
199 RCBA32(0x3418) |= (1 << 0);
200 RCBA16(0x0200) = 0x2008;
201 RCBA8(0x2027) = 0x0d;
202 RCBA16(0x3e08) |= (1 << 7);
203 RCBA16(0x3e48) |= (1 << 7);
204 RCBA32(0x3e0e) |= (1 << 7);
205 RCBA32(0x3e4e) |= (1 << 7);
207 // next step only on ich7m b0 and later:
208 reg32 = RCBA32(0x2034);
209 reg32 &= ~(0x0f << 16);
211 RCBA32(0x2034) = reg32;
216 // Now, this needs to be included because it relies on the symbol
217 // __PRE_RAM__ being set during CAR stage (in order to compile the
218 // BSS free versions of the functions). Either rewrite the code
219 // to be always BSS free, or invent a flag that's better suited than
220 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
222 #include "lib/cbmem.c"
224 void main(unsigned long bist)
234 early_superio_config_lpc47m15x();
236 /* Set up the console */
239 #if CONFIG_USBDEBUG_DIRECT
240 i82801gx_enable_usbdebug(DBGP_DEFAULT);
241 early_usbdebug_init();
246 /* Halt if there was a built in self test failure */
247 report_bist_failure(bist);
249 if (MCHBAR16(SSKPD) == 0xCAFE) {
250 printk(BIOS_DEBUG, "soft reset detected.\n");
254 /* Perform some early chipset initialization required
255 * before RAM initialization can work
257 i945_early_initialization();
260 reg32 = inl(DEFAULT_PMBASE + 0x04);
261 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
262 if (((reg32 >> 10) & 7) == 5) {
263 #if CONFIG_HAVE_ACPI_RESUME
264 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
266 /* Clear SLP_TYPE. This will break stage2 but
267 * we care for that when we get there.
269 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
271 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
275 /* Enable SPD ROMs and DDR-II DRAM */
278 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
279 dump_spd_registers();
282 sdram_initialize(boot_mode);
284 /* Perform some initialization that must run before stage2 */
287 /* This should probably go away. Until now it is required
288 * and mainboard specific
292 /* Chipset Errata! */
295 /* Initialize the internal PCIe links before we go into stage2 */
296 i945_late_initialization();
298 #if !CONFIG_HAVE_ACPI_RESUME
299 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
300 #if defined(DEBUG_RAM_SETUP)
301 sdram_dump_mchbar_registers();
305 /* This will not work if TSEG is in place! */
306 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
308 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
309 ram_check(0x00000000, 0x000a0000);
310 //ram_check(0x00100000, tom);
315 MCHBAR16(SSKPD) = 0xCAFE;
317 #if CONFIG_HAVE_ACPI_RESUME
318 /* Start address of high memory tables */
319 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
321 /* If there is no high memory area, we didn't boot before, so
322 * this is not a resume. In that case we just create the cbmem toc.
324 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
325 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
327 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
328 * through stage 2. We could keep stuff like stack and heap in high tables
329 * memory completely, but that's a wonderful clean up task for another
332 if (resume_backup_memory)
333 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
335 /* Magic for S3 resume */
336 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);