src/mainboard/intel/d945gclf/cmos.layout

   1 #
   2 # This file is part of the coreboot project.
   3 #
   4 # Copyright (C) 2007-2008 coresystems GmbH
   5 #
   6 # This program is free software; you can redistribute it and/or
   7 # modify it under the terms of the GNU General Public License as
   8 # published by the Free Software Foundation; version 2 of the License.
   9 #
  10 # This program is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 # GNU General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU General Public License
  16 # along with this program; if not, write to the Free Software
  17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 #
  19
  20 # -----------------------------------------------------------------
  21 entries
  22
  23 #start-bit length  config config-ID    name
  24 #0            8       r       0        seconds
  25 #8            8       r       0        alarm_seconds
  26 #16           8       r       0        minutes
  27 #24           8       r       0        alarm_minutes
  28 #32           8       r       0        hours
  29 #40           8       r       0        alarm_hours
  30 #48           8       r       0        day_of_week
  31 #56           8       r       0        day_of_month
  32 #64           8       r       0        month
  33 #72           8       r       0        year
  34 # -----------------------------------------------------------------
  35 # Status Register A
  36 #80           4       r       0        rate_select
  37 #84           3       r       0        REF_Clock
  38 #87           1       r       0        UIP
  39 # -----------------------------------------------------------------
  40 # Status Register B
  41 #88           1       r       0        auto_switch_DST
  42 #89           1       r       0        24_hour_mode
  43 #90           1       r       0        binary_values_enable
  44 #91           1       r       0        square-wave_out_enable
  45 #92           1       r       0        update_finished_enable
  46 #93           1       r       0        alarm_interrupt_enable
  47 #94           1       r       0        periodic_interrupt_enable
  48 #95           1       r       0        disable_clock_updates
  49 # -----------------------------------------------------------------
  50 # Status Register C
  51 #96           4       r       0        status_c_rsvd
  52 #100          1       r       0        uf_flag
  53 #101          1       r       0        af_flag
  54 #102          1       r       0        pf_flag
  55 #103          1       r       0        irqf_flag
  56 # -----------------------------------------------------------------
  57 # Status Register D
  58 #104          7       r       0        status_d_rsvd
  59 #111          1       r       0        valid_cmos_ram
  60 # -----------------------------------------------------------------
  61 # Diagnostic Status Register
  62 #112          8       r       0        diag_rsvd1
  63
  64 # -----------------------------------------------------------------
  65 0          120       r       0        reserved_memory
  66 #120        264       r       0        unused
  67
  68 # -----------------------------------------------------------------
  69 # RTC_BOOT_BYTE (coreboot hardcoded)
  70 384          1       e       4        boot_option
  71 385          1       e       4        last_boot
  72 388          4       r       0        reboot_bits
  73 #390          2       r       0        unused?
  74
  75 # -----------------------------------------------------------------
  76 # coreboot config options: console
  77 392          3       e       5        baud_rate
  78 395          4       e       6        debug_level
  79 #399          1       r       0        unused
  80
  81 # coreboot config options: cpu
  82 400          1       e       2        hyper_threading
  83 #401          7       r       0        unused
  84
  85 # coreboot config options: southbridge
  86 408          1       e       1        nmi
  87 409          2       e       7        power_on_after_fail
  88 #411          5       r       0        unused
  89
  90 # coreboot config options: bootloader
  91 416        512       s       0        boot_devices
  92 #928         80       r       0        unused
  93
  94 # coreboot config options: check sums
  95 984         16       h       0        check_sum
  96 #1000        24       r       0        amd_reserved
  97
  98 # ram initialization internal data
  99 1024         8       r       0        C0WL0REOST
 100 1032         8       r       0        C1WL0REOST
 101 1040         8       r       0        RCVENMT
 102 1048         4       r       0        C0DRT1
 103 1052         4       r       0        C1DRT1
 104
 105 # -----------------------------------------------------------------
 106
 107 enumerations
 108
 109 #ID value   text
 110 1     0     Disable
 111 1     1     Enable
 112 2     0     Enable
 113 2     1     Disable
 114 4     0     Fallback
 115 4     1     Normal
 116 5     0     115200
 117 5     1     57600
 118 5     2     38400
 119 5     3     19200
 120 5     4     9600
 121 5     5     4800
 122 5     6     2400
 123 5     7     1200
 124 6     1     Emergency
 125 6     2     Alert
 126 6     3     Critical
 127 6     4     Error
 128 6     5     Warning
 129 6     6     Notice
 130 6     7     Info
 131 6     8     Debug
 132 6     9     Spew
 133 7     0     Disable
 134 7     1     Enable
 135 7     2     Keep
 136
 137 # -----------------------------------------------------------------
 138 checksums
 139
 140 checksum 392 983 984
 141
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