2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## XIP_ROM_SIZE must be a power of 2.
22 default XIP_ROM_SIZE = 64 * 1024
23 include /config/nofailovercalculation.lb
30 # Compile cache_as_ram.c to auto.inc.
31 makerule ./cache_as_ram_auto.inc
32 # depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
33 depends "$(MAINBOARD)/cache_as_ram_auto.c"
34 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
35 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
36 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
38 mainboardinit cpu/x86/16bit/entry16.inc
39 mainboardinit cpu/x86/32bit/entry32.inc
40 ldscript /cpu/x86/16bit/entry16.lds
41 ldscript /cpu/x86/32bit/entry32.lds
43 mainboardinit cpu/x86/16bit/reset16.inc
44 ldscript /cpu/x86/16bit/reset16.lds
46 mainboardinit cpu/x86/32bit/reset32.inc
47 ldscript /cpu/x86/32bit/reset32.lds
49 mainboardinit arch/i386/lib/id.inc
50 ldscript /arch/i386/lib/id.lds
52 ldscript /arch/i386/lib/failover.lds
53 # mainboardinit ./failover.inc
55 mainboardinit cpu/x86/fpu/enable_fpu.inc
56 mainboardinit cpu/amd/model_lx/cache_as_ram.inc
57 mainboardinit ./cache_as_ram_auto.inc
61 chip northbridge/amd/lx
62 device pci_domain 0 on
63 device pci 1.0 on end # Northbridge
64 device pci 1.1 on end # Graphics
65 chip southbridge/amd/cs5536
66 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
67 # SIRQ Mode = Active(Quiet) mode. Save power....
68 # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
69 register "lpc_serirq_enable" = "0x0000105a"
70 register "lpc_serirq_polarity" = "0x0000EFA5"
71 register "lpc_serirq_mode" = "1"
72 register "enable_gpio_int_route" = "0x0D0C0700"
73 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
74 register "enable_USBP4_device" = "1" # 0: host, 1:device
75 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
76 register "com1_enable" = "0"
77 register "com1_address" = "0x3F8"
78 register "com1_irq" = "4"
79 register "com2_enable" = "0"
80 register "com2_address" = "0x2F8"
81 register "com2_irq" = "3"
82 register "unwanted_vpci[0]" = "0" # End of list has a zero
83 device pci 9.0 on end # Slot1
84 device pci a.0 on end # Slot2
85 device pci b.0 on end # Slot3
86 device pci c.0 on end # Slot4
87 device pci e.0 on end # Ethernet 0
88 device pci 10.0 on end # Ethernet 1
89 device pci 11.0 on end # SATA
90 device pci f.0 on # ISA Bridge
91 chip superio/winbond/w83627hf
92 device pnp 2e.0 off # Floppy
97 device pnp 2e.1 off # Parallel port
101 device pnp 2e.2 on # Com1
105 device pnp 2e.3 on # Com2
109 device pnp 2e.5 on # Keyboard
115 device pnp 2e.6 off end # CIR
116 device pnp 2e.7 off end # GAME_MIDI_GIPO1
117 device pnp 2e.8 off end # GPIO2
118 device pnp 2e.9 off end # GPIO3
119 device pnp 2e.a off end # ACPI
120 device pnp 2e.b off end # HW Monitor
123 device pci f.2 on end # IDE Controller
124 device pci f.3 on end # Audio
125 device pci f.4 on end # OHCI
126 device pci f.5 on end # EHCI
129 # APIC cluster is late CPU init.
130 device apic_cluster 0 on
131 chip cpu/amd/model_lx