1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_HAVE_OPTION_TABLE
7 uses CONFIG_USE_OPTION_TABLE
8 uses CONFIG_ROM_PAYLOAD
9 uses CONFIG_IRQ_SLOT_COUNT
11 uses CONFIG_MAINBOARD_VENDOR
12 uses CONFIG_MAINBOARD_PART_NUMBER
13 uses COREBOOT_EXTRA_VERSION
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_STACK_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_IMAGE_SIZE
21 uses CONFIG_ROM_SECTION_SIZE
22 uses CONFIG_ROM_SECTION_OFFSET
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_HAVE_MP_TABLE
28 uses CONFIG_CROSS_COMPILE
32 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
33 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
34 uses CONFIG_CONSOLE_SERIAL8250
35 uses CONFIG_TTYS0_BAUD
36 uses CONFIG_TTYS0_BASE
38 uses CONFIG_UDELAY_TSC
39 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
40 uses CONFIG_CONSOLE_VGA
41 uses CONFIG_PCI_ROM_RUN
42 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
43 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
44 uses CONFIG_PRECOMPRESSED_PAYLOAD
46 uses CONFIG_PIRQ_ROUTE
48 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
49 default CONFIG_ROM_SIZE = 256*1024
56 default CONFIG_CONSOLE_VGA=1
57 default CONFIG_PCI_ROM_RUN=1
60 ## Build code for the fallback boot
62 default CONFIG_HAVE_FALLBACK_BOOT=0
67 default CONFIG_HAVE_MP_TABLE=0
70 ## Build code to reset the motherboard from coreboot
72 default CONFIG_HAVE_HARD_RESET=0
74 ## Delay timer options
76 default CONFIG_UDELAY_TSC=1
77 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
80 ## Build code to export a programmable irq routing table
82 default CONFIG_HAVE_PIRQ_TABLE=1
83 default CONFIG_IRQ_SLOT_COUNT=5
84 default CONFIG_PIRQ_ROUTE=1
88 ## Build code to export a CMOS option table
90 default CONFIG_HAVE_OPTION_TABLE=1
93 ### coreboot layout values
96 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
97 default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
98 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
101 ## Use a small 8K stack
103 default CONFIG_STACK_SIZE=0x2000
106 ## Use a small 16K heap
108 default CONFIG_HEAP_SIZE=0x4000
111 ## Only use the option table in a normal image
113 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
114 default CONFIG_USE_OPTION_TABLE = 0
116 default CONFIG_RAMBASE = 0x00004000
118 default CONFIG_ROM_PAYLOAD = 1
121 ## The default compiler
123 default CONFIG_CROSS_COMPILE=""
124 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
128 ## The Serial Console
131 # To Enable the Serial Console
132 default CONFIG_CONSOLE_SERIAL8250=1
134 ## Select the serial console baud rate
135 default CONFIG_TTYS0_BAUD=115200
136 #default CONFIG_TTYS0_BAUD=57600
137 #default CONFIG_TTYS0_BAUD=38400
138 #default CONFIG_TTYS0_BAUD=19200
139 #default CONFIG_TTYS0_BAUD=9600
140 #default CONFIG_TTYS0_BAUD=4800
141 #default CONFIG_TTYS0_BAUD=2400
142 #default CONFIG_TTYS0_BAUD=1200
144 # Select the serial console base port
145 default CONFIG_TTYS0_BASE=0x3f8
147 # Select the serial protocol
148 # This defaults to 8 data bits, 1 stop bit, and no parity
149 default CONFIG_TTYS0_LCS=0x3
152 ### Select the coreboot loglevel
154 ## EMERG 1 system is unusable
155 ## ALERT 2 action must be taken immediately
156 ## CRIT 3 critical conditions
157 ## ERR 4 error conditions
158 ## WARNING 5 warning conditions
159 ## NOTICE 6 normal but significant condition
160 ## INFO 7 informational
161 ## CONFIG_DEBUG 8 debug-level messages
162 ## SPEW 9 Way too many details
164 ## Request this level of debugging output
165 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
167 ## At a maximum only compile in this level of debugging
168 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
170 default CONFIG_VIDEO_MB = 0