1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 128 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
7 ## Set all of the defaults for an x86 architecture
13 ## Build the objects we have code for in this directory.
18 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
25 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
26 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
29 makerule ./failover.inc
30 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
31 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
35 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
36 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
39 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
40 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
44 ## Build our 16 bit and 32 bit coreboot entry code
46 mainboardinit cpu/x86/16bit/entry16.inc
47 mainboardinit cpu/x86/32bit/entry32.inc
48 ldscript /cpu/x86/16bit/entry16.lds
49 ldscript /cpu/x86/32bit/entry32.lds
52 ## Build our reset vector (This is where coreboot is entered)
54 if CONFIG_USE_FALLBACK_IMAGE
55 mainboardinit cpu/x86/16bit/reset16.inc
56 ldscript /cpu/x86/16bit/reset16.lds
58 mainboardinit cpu/x86/32bit/reset32.inc
59 ldscript /cpu/x86/32bit/reset32.lds
62 ### Should this be in the northbridge code?
63 mainboardinit arch/i386/lib/cpu_reset.inc
66 ## Include an id string (For safe flashing)
68 mainboardinit arch/i386/lib/id.inc
69 ldscript /arch/i386/lib/id.lds
72 ### This is the early phase of coreboot startup
73 ### Things are delicate and we test to see if we should
74 ### failover to another image.
76 if CONFIG_USE_FALLBACK_IMAGE
77 ldscript /arch/i386/lib/failover.lds
78 mainboardinit ./failover.inc
82 ### O.k. We aren't just an intermediary anymore!
88 mainboardinit cpu/x86/fpu/enable_fpu.inc
89 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
90 mainboardinit cpu/amd/model_gx1/gx_setup.inc
91 mainboardinit ./auto.inc
94 ## Include the secondary Configuration files
99 chip northbridge/amd/gx1
100 device pci_domain 0 on
101 device pci 0.0 on end
102 chip southbridge/amd/cs5530
103 device pci 0a.0 on end # ETH0
104 device pci 0b.0 off end # ETH1
105 device pci 0c.0 on end # ETH2
106 device pci 0f.0 on end # PCI slot
108 chip superio/winbond/w83977tf
109 device pnp 2e.0 on # FDC
112 device pnp 2e.1 on # Parallel Port
116 device pnp 2e.2 on # COM1
120 register "com1" = "{115200}"
121 device pnp 2e.3 on # COM2
125 register "com2" = "{115200}"
126 device pnp 2e.4 off # Reserved
128 device pnp 2e.5 on # Keyboard
131 irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
132 irq 0x72 = 0x0c # Int 12 for PS/2 mouse
134 device pnp 2e.6 on # IR
138 device pnp 2e.7 on # GAME/MIDI/GPIO1
141 device pnp 2e.8 on # GPIO2
144 device pnp 2e.9 on # GPIO3
147 device pnp 2e.A on # Power Management
151 device pci 12.1 on end # SMI
152 device pci 12.2 on end # IDE
153 device pci 12.3 on end # Audio
154 device pci 12.4 on end # VGA onboard
156 device pci 13.0 on end # USB
160 chip cpu/amd/model_gx1