1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 128 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
7 ## Set all of the defaults for an x86 architecture
13 ## Build the objects we have code for in this directory.
18 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
24 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
25 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
28 makerule ./failover.inc
29 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
30 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
34 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
35 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
38 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
39 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
43 ## Build our 16 bit and 32 bit coreboot entry code
45 mainboardinit cpu/x86/16bit/entry16.inc
46 mainboardinit cpu/x86/32bit/entry32.inc
47 ldscript /cpu/x86/16bit/entry16.lds
48 ldscript /cpu/x86/32bit/entry32.lds
51 ## Build our reset vector (This is where coreboot is entered)
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/reset16.inc
55 ldscript /cpu/x86/16bit/reset16.lds
57 mainboardinit cpu/x86/32bit/reset32.inc
58 ldscript /cpu/x86/32bit/reset32.lds
61 ### Should this be in the northbridge code?
62 mainboardinit arch/i386/lib/cpu_reset.inc
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
71 ### This is the early phase of coreboot startup
72 ### Things are delicate and we test to see if we should
73 ### failover to another image.
75 if CONFIG_USE_FALLBACK_IMAGE
76 ldscript /arch/i386/lib/failover.lds
77 mainboardinit ./failover.inc
81 ### O.k. We aren't just an intermediary anymore!
87 mainboardinit cpu/x86/fpu_enable.inc
88 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
89 mainboardinit cpu/amd/model_gx1/gx_setup.inc
90 mainboardinit ./auto.inc
93 ## Include the secondary Configuration files
98 chip northbridge/amd/gx1
99 device pci_domain 0 on
100 device pci 0.0 on end
101 chip southbridge/amd/cs5530
102 device pci 0a.0 on end # ETH0
103 device pci 0b.0 off end # ETH1
104 device pci 0c.0 on end # ETH2
105 device pci 0f.0 on end # PCI slot
107 chip superio/winbond/w83977tf
108 device pnp 2e.0 on # FDC
111 device pnp 2e.1 on # Parallel Port
115 device pnp 2e.2 on # COM1
119 register "com1" = "{115200}"
120 device pnp 2e.3 on # COM2
124 register "com2" = "{115200}"
125 device pnp 2e.4 off # Reserved
127 device pnp 2e.5 on # Keyboard
130 irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
131 irq 0x72 = 0x0c # Int 12 for PS/2 mouse
133 device pnp 2e.6 on # IR
137 device pnp 2e.7 on # GAME/MIDI/GPIO1
140 device pnp 2e.8 on # GPIO2
143 device pnp 2e.9 on # GPIO3
146 device pnp 2e.A on # Power Management
150 device pci 12.1 on end # SMI
151 device pci 12.2 on end # IDE
152 device pci 12.3 on end # Audio
153 device pci 12.4 on end # VGA onboard
155 device pci 13.0 on end # USB
159 chip cpu/amd/model_gx1