2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
24 #include "routing.asl"
28 /* Routing is in System Bus scope */
32 /* Bus 0, Dev 0 - RS780 Host Controller */
33 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
34 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
35 Package(){0x0002FFFF, 0, INTC, 0 },
36 Package(){0x0002FFFF, 1, INTD, 0 },
37 Package(){0x0002FFFF, 2, INTA, 0 },
38 Package(){0x0002FFFF, 3, INTB, 0 },
39 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
40 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
41 Package(){0x0004FFFF, 0, INTA, 0 },
42 Package(){0x0004FFFF, 1, INTB, 0 },
43 Package(){0x0004FFFF, 2, INTC, 0 },
44 Package(){0x0004FFFF, 3, INTD, 0 },
45 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
46 /* Package(){0x0005FFFF, 0, INTB, 0 }, */
47 /* Package(){0x0005FFFF, 1, INTC, 0 }, */
48 /* Package(){0x0005FFFF, 2, INTD, 0 }, */
49 /* Package(){0x0005FFFF, 3, INTA, 0 }, */
50 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
51 Package(){0x0006FFFF, 0, INTC, 0 },
52 Package(){0x0006FFFF, 1, INTD, 0 },
53 Package(){0x0006FFFF, 2, INTA, 0 },
54 Package(){0x0006FFFF, 3, INTB, 0 },
55 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
56 Package(){0x0007FFFF, 0, INTD, 0 },
57 Package(){0x0007FFFF, 1, INTA, 0 },
58 Package(){0x0007FFFF, 2, INTB, 0 },
59 Package(){0x0007FFFF, 3, INTC, 0 },
60 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
63 /* Bus 0, Dev 17 - SATA controller #2 */
64 /* Bus 0, Dev 18 - SATA controller #1 */
65 Package(){0x0011FFFF, 0, INTA, 0 },
67 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
68 * EHCI, dev 18, 19 func 2 */
69 Package(){0x0012FFFF, 0, INTA, 0 },
70 Package(){0x0012FFFF, 1, INTB, 0 },
71 Package(){0x0012FFFF, 2, INTC, 0 },
73 Package(){0x0013FFFF, 0, INTC, 0 },
74 Package(){0x0013FFFF, 1, INTD, 0 },
75 Package(){0x0013FFFF, 2, INTA, 0 },
77 /* Package(){0x0014FFFF, 1, INTA, 0 }, */
79 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
80 Package(){0x0014FFFF, 0, INTA, 0 },
81 Package(){0x0014FFFF, 1, INTB, 0 },
82 Package(){0x0014FFFF, 2, INTC, 0 },
83 Package(){0x0014FFFF, 3, INTD, 0 },
87 /* NB devices in APIC mode */
88 /* Bus 0, Dev 0 - RS780 Host Controller */
90 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
91 /* Package(){0x0001FFFF, 0, 0, 18 }, */
92 /* package(){0x0001FFFF, 1, 0, 19 }, */
94 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
95 Package(){0x0002FFFF, 0, 0, 18 },
96 /* Package(){0x0002FFFF, 1, 0, 19 }, */
97 /* Package(){0x0002FFFF, 2, 0, 16 }, */
98 /* Package(){0x0002FFFF, 3, 0, 17 }, */
100 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
101 Package(){0x0003FFFF, 0, 0, 19 },
103 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
104 Package(){0x0004FFFF, 0, 0, 16 },
105 /* Package(){0x0004FFFF, 1, 0, 17 }, */
106 /* Package(){0x0004FFFF, 2, 0, 18 }, */
107 /* Package(){0x0004FFFF, 3, 0, 19 }, */
109 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
110 /* Package(){0x0005FFFF, 0, 0, 17 }, */
111 /* Package(){0x0005FFFF, 1, 0, 18 }, */
112 /* Package(){0x0005FFFF, 2, 0, 19 }, */
113 /* Package(){0x0005FFFF, 3, 0, 16 }, */
115 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
116 /* Package(){0x0006FFFF, 0, 0, 18 }, */
117 /* Package(){0x0006FFFF, 1, 0, 19 }, */
118 /* Package(){0x0006FFFF, 2, 0, 16 }, */
119 /* Package(){0x0006FFFF, 3, 0, 17 }, */
121 /* Bus 0, Dev 7 - PCIe Bridge for network card */
122 /* Package(){0x0007FFFF, 0, 0, 19 }, */
123 /* Package(){0x0007FFFF, 1, 0, 16 }, */
124 /* Package(){0x0007FFFF, 2, 0, 17 }, */
125 /* Package(){0x0007FFFF, 3, 0, 18 }, */
127 /* Bus 0, Dev 9 - PCIe Bridge for network card */
128 Package(){0x0009FFFF, 0, 0, 17 },
129 /* Package(){0x0009FFFF, 1, 0, 16 }, */
130 /* Package(){0x0009FFFF, 2, 0, 17 }, */
131 /* Package(){0x0009FFFF, 3, 0, 18 }, */
132 /* Bus 0, Dev A - PCIe Bridge for network card */
133 Package(){0x000AFFFF, 0, 0, 18 },
134 /* Package(){0x000AFFFF, 1, 0, 16 }, */
135 /* Package(){0x000AFFFF, 2, 0, 17 }, */
136 /* Package(){0x000AFFFF, 3, 0, 18 }, */
137 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
139 /* SB devices in APIC mode */
140 /* Bus 0, Dev 17 - SATA controller #2 */
141 /* Bus 0, Dev 18 - SATA controller #1 */
142 Package(){0x0011FFFF, 0, 0, 22 },
144 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
145 * EHCI, dev 18, 19 func 2 */
146 Package(){0x0012FFFF, 0, 0, 16 },
147 Package(){0x0012FFFF, 1, 0, 17 },
148 Package(){0x0012FFFF, 2, 0, 18 },
150 Package(){0x0013FFFF, 0, 0, 18 },
151 Package(){0x0013FFFF, 1, 0, 19 },
152 Package(){0x0013FFFF, 2, 0, 16 },
154 /* Package(){0x00140000, 0, 0, 16 }, */
156 /* Package(){0x00130004, 2, 0, 18 }, */
157 /* Package(){0x00130005, 3, 0, 19 }, */
159 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
160 Package(){0x0014FFFF, 0, 0, 16 },
161 Package(){0x0014FFFF, 1, 0, 17 },
162 Package(){0x0014FFFF, 2, 0, 18 },
163 Package(){0x0014FFFF, 3, 0, 19 },
164 /* Package(){0x00140004, 2, 0, 18 }, */
165 /* Package(){0x00140004, 3, 0, 19 }, */
166 /* Package(){0x00140005, 1, 0, 17 }, */
167 /* Package(){0x00140006, 1, 0, 17 }, */
171 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
172 Package(){0x0005FFFF, 0, INTA, 0 },
173 Package(){0x0005FFFF, 1, INTB, 0 },
174 Package(){0x0005FFFF, 2, INTC, 0 },
175 Package(){0x0005FFFF, 3, INTD, 0 },
178 Name(APR1, Package(){
179 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
180 Package(){0x0005FFFF, 0, 0, 18 },
181 Package(){0x0005FFFF, 1, 0, 19 },
182 /* Package(){0x0005FFFF, 2, 0, 20 }, */
183 /* Package(){0x0005FFFF, 3, 0, 17 }, */
187 /* The external GFX - Hooked to PCIe slot 2 */
188 Package(){0x0000FFFF, 0, INTC, 0 },
189 Package(){0x0000FFFF, 1, INTD, 0 },
190 Package(){0x0000FFFF, 2, INTA, 0 },
191 Package(){0x0000FFFF, 3, INTB, 0 },
194 Name(APS2, Package(){
195 /* The external GFX - Hooked to PCIe slot 2 */
196 Package(){0x0000FFFF, 0, 0, 18 },
197 Package(){0x0000FFFF, 1, 0, 19 },
198 Package(){0x0000FFFF, 2, 0, 16 },
199 Package(){0x0000FFFF, 3, 0, 17 },
203 /* PCIe slot - Hooked to PCIe slot 4 */
204 Package(){0x0000FFFF, 0, INTA, 0 },
205 Package(){0x0000FFFF, 1, INTB, 0 },
206 Package(){0x0000FFFF, 2, INTC, 0 },
207 Package(){0x0000FFFF, 3, INTD, 0 },
210 Name(APS4, Package(){
211 /* PCIe slot - Hooked to PCIe slot 4 */
212 Package(){0x0000FFFF, 0, 0, 16 },
213 Package(){0x0000FFFF, 1, 0, 17 },
214 Package(){0x0000FFFF, 2, 0, 18 },
215 Package(){0x0000FFFF, 3, 0, 19 },
219 /* PCIe slot - Hooked to PCIe slot 5 */
220 Package(){0x0000FFFF, 0, INTB, 0 },
221 Package(){0x0000FFFF, 1, INTC, 0 },
222 Package(){0x0000FFFF, 2, INTD, 0 },
223 Package(){0x0000FFFF, 3, INTA, 0 },
226 Name(APS5, Package(){
227 /* PCIe slot - Hooked to PCIe slot 5 */
228 Package(){0x0000FFFF, 0, 0, 17 },
229 Package(){0x0000FFFF, 1, 0, 18 },
230 Package(){0x0000FFFF, 2, 0, 19 },
231 Package(){0x0000FFFF, 3, 0, 16 },
235 /* PCIe slot - Hooked to PCIe slot 6 */
236 Package(){0x0000FFFF, 0, INTC, 0 },
237 Package(){0x0000FFFF, 1, INTD, 0 },
238 Package(){0x0000FFFF, 2, INTA, 0 },
239 Package(){0x0000FFFF, 3, INTB, 0 },
242 Name(APS6, Package(){
243 /* PCIe slot - Hooked to PCIe slot 6 */
244 Package(){0x0000FFFF, 0, 0, 18 },
245 Package(){0x0000FFFF, 1, 0, 19 },
246 Package(){0x0000FFFF, 2, 0, 16 },
247 Package(){0x0000FFFF, 3, 0, 17 },
251 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
252 Package(){0x0000FFFF, 0, INTD, 0 },
253 Package(){0x0000FFFF, 1, INTA, 0 },
254 Package(){0x0000FFFF, 2, INTB, 0 },
255 Package(){0x0000FFFF, 3, INTC, 0 },
258 Name(APS7, Package(){
259 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
260 Package(){0x0000FFFF, 0, 0, 19 },
261 Package(){0x0000FFFF, 1, 0, 16 },
262 Package(){0x0000FFFF, 2, 0, 17 },
263 Package(){0x0000FFFF, 3, 0, 18 },
266 /* PCIe slot - Hooked to PCIe slot 9 */
267 Package(){0x0000FFFF, 0, INTD, 0 },
268 Package(){0x0000FFFF, 1, INTA, 0 },
269 Package(){0x0000FFFF, 2, INTB, 0 },
270 Package(){0x0000FFFF, 3, INTC, 0 },
273 Name(APS9, Package(){
274 /* PCIe slot - Hooked to PCIe slot 9 */
275 Package(){0x0000FFFF, 0, 0, 17 },
276 Package(){0x0000FFFF, 1, 0, 18 },
277 Package(){0x0000FFFF, 2, 0, 19 },
278 Package(){0x0000FFFF, 3, 0, 16 },
281 /* PCIe slot - Hooked to PCIe slot 10 */
282 Package(){0x0000FFFF, 0, INTD, 0 },
283 Package(){0x0000FFFF, 1, INTA, 0 },
284 Package(){0x0000FFFF, 2, INTB, 0 },
285 Package(){0x0000FFFF, 3, INTC, 0 },
288 Name(APSa, Package(){
289 /* PCIe slot - Hooked to PCIe slot 10 */
290 Package(){0x0000FFFF, 0, 0, 18 },
291 Package(){0x0000FFFF, 1, 0, 19 },
292 Package(){0x0000FFFF, 2, 0, 16 },
293 Package(){0x0000FFFF, 3, 0, 17 },
296 Name(PCIB, Package(){
297 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
298 Package(){0x0005FFFF, 0, 0, 0x14 },
299 Package(){0x0005FFFF, 1, 0, 0x15 },
300 Package(){0x0005FFFF, 2, 0, 0x16 },
301 Package(){0x0005FFFF, 3, 0, 0x17 },
302 Package(){0x0006FFFF, 0, 0, 0x15 },
303 Package(){0x0006FFFF, 1, 0, 0x16 },
304 Package(){0x0006FFFF, 2, 0, 0x17 },
305 Package(){0x0006FFFF, 3, 0, 0x14 },
306 Package(){0x0007FFFF, 0, 0, 0x16 },
307 Package(){0x0007FFFF, 1, 0, 0x17 },
308 Package(){0x0007FFFF, 2, 0, 0x14 },
309 Package(){0x0007FFFF, 3, 0, 0x15 },