2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
5 default CONFIG_ROM_SIZE = 256 * 1024
8 ## Compute where this copy of coreboot will start in the boot rom
10 default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
13 ## Compute a range of ROM that can cached to speed up coreboot,
16 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
17 ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
19 default CONFIG_XIP_ROM_SIZE=65536
20 default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
23 ## Set all of the defaults for an x86 architecture
29 ## Build the objects we have code for in this directory.
34 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
40 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
41 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
44 makerule ./failover.inc
45 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
46 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
50 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
51 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
54 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
55 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
59 ## Build our 16 bit and 32 bit coreboot entry code
61 mainboardinit cpu/x86/16bit/entry16.inc
62 mainboardinit cpu/x86/32bit/entry32.inc
63 ldscript /cpu/x86/16bit/entry16.lds
64 ldscript /cpu/x86/32bit/entry32.lds
67 ## Build our reset vector (This is where coreboot is entered)
69 mainboardinit cpu/x86/16bit/reset16.inc
70 ldscript /cpu/x86/16bit/reset16.lds
72 ### Should this be in the northbridge code?
73 mainboardinit arch/i386/lib/cpu_reset.inc
76 ## Include an id string (For safe flashing)
78 mainboardinit arch/i386/lib/id.inc
79 ldscript /arch/i386/lib/id.lds
82 ### O.k. We aren't just an intermediary anymore!
88 mainboardinit cpu/x86/fpu_enable.inc
89 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
90 mainboardinit cpu/amd/model_gx1/gx_setup.inc
91 mainboardinit ./auto.inc
94 ## Include the secondary Configuration files
99 chip northbridge/amd/gx1
100 device pci_domain 0 on
101 device pci 0.0 on end
102 chip southbridge/amd/cs5530
105 chip superio/winbond/w83977f
106 device pnp 3f0.0 on # FDC
109 device pnp 3f0.1 on # Parallel port
113 device pnp 3f0.2 on # COM1
117 register "com1" = "{115200}"
118 device pnp 3f0.3 on # COM2
122 register "com2" = "{115200}"
123 device pnp 3f0.4 on # RTC
127 device pnp 3f0.5 on # Keyboard
130 irq 0x70 = 1 # Int 1 for PS/2 keyboard
131 irq 0x72 = 12 # Int 12 for PS/2 mouse
133 device pnp 3f0.6 off # IR
135 device pnp 3f0.7 off # GPIO1
137 device pnp 3f0.8 off # GPIO
140 device pci 12.1 on end # SMI
141 device pci 12.2 on end # IDE
142 device pci 12.3 on end # Audio
143 device pci 12.4 on end # VGA onboard
147 device pci 0e.0 on end # ETH0
148 device pci 13.0 on end # USB
153 chip cpu/amd/model_gx1