2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
5 default CONFIG_ROM_SIZE = 256 * 1024
8 ## Compute where this copy of coreboot will start in the boot rom
10 default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
13 ## Compute a range of ROM that can cached to speed up coreboot,
16 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
17 ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
19 default CONFIG_XIP_ROM_SIZE=65536
20 default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
23 ## Set all of the defaults for an x86 architecture
29 ## Build the objects we have code for in this directory.
34 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
41 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
42 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
45 makerule ./failover.inc
46 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
47 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
51 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
52 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
55 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
56 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
60 ## Build our 16 bit and 32 bit coreboot entry code
62 mainboardinit cpu/x86/16bit/entry16.inc
63 mainboardinit cpu/x86/32bit/entry32.inc
64 ldscript /cpu/x86/16bit/entry16.lds
65 ldscript /cpu/x86/32bit/entry32.lds
68 ## Build our reset vector (This is where coreboot is entered)
70 mainboardinit cpu/x86/16bit/reset16.inc
71 ldscript /cpu/x86/16bit/reset16.lds
73 ### Should this be in the northbridge code?
74 mainboardinit arch/i386/lib/cpu_reset.inc
77 ## Include an id string (For safe flashing)
79 mainboardinit arch/i386/lib/id.inc
80 ldscript /arch/i386/lib/id.lds
83 ### O.k. We aren't just an intermediary anymore!
89 mainboardinit cpu/x86/fpu/enable_fpu.inc
90 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
91 mainboardinit cpu/amd/model_gx1/gx_setup.inc
92 mainboardinit ./auto.inc
95 ## Include the secondary Configuration files
100 chip northbridge/amd/gx1
101 device pci_domain 0 on
102 device pci 0.0 on end
103 chip southbridge/amd/cs5530
106 chip superio/winbond/w83977f
107 device pnp 3f0.0 on # FDC
110 device pnp 3f0.1 on # Parallel port
114 device pnp 3f0.2 on # COM1
118 register "com1" = "{115200}"
119 device pnp 3f0.3 on # COM2
123 register "com2" = "{115200}"
124 device pnp 3f0.4 on # RTC
128 device pnp 3f0.5 on # Keyboard
131 irq 0x70 = 1 # Int 1 for PS/2 keyboard
132 irq 0x72 = 12 # Int 12 for PS/2 mouse
134 device pnp 3f0.6 off # IR
136 device pnp 3f0.7 off # GPIO1
138 device pnp 3f0.8 off # GPIO
141 device pci 12.1 on end # SMI
142 device pci 12.2 on end # IDE
143 device pci 12.3 on end # Audio
144 device pci 12.4 on end # VGA onboard
148 device pci 0e.0 on end # ETH0
149 device pci 13.0 on end # USB
154 chip cpu/amd/model_gx1