src/mainboard/ibm/e326/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "northbridge/amd/amdk8/debug.c"
  20 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/setup_resource_map.c"
  24 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  25 #include <spd.h>
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31         if (is_cpu_pre_c0()) {
  32                 /* Set the memreset low */
  33                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  34                 /* Ensure the BIOS has control of the memory lines */
  35                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  36         } else {
  37                 /* Ensure the CPU has controll of the memory lines */
  38                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  39         }
  40 }
  41
  42 static void memreset(int controllers, const struct mem_controller *ctrl)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 udelay(800);
  46                 /* Set memreset_high */
  47                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  48                 udelay(90);
  49         }
  50 }
  51
  52 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  53 {
  54         /* nothing to do */
  55 }
  56
  57 static inline int spd_read_byte(unsigned device, unsigned address)
  58 {
  59         return smbus_read_byte(device, address);
  60 }
  61
  62 #include "northbridge/amd/amdk8/raminit.c"
  63 #include "resourcemap.c"
  64 #include "northbridge/amd/amdk8/coherent_ht.c"
  65 #include "lib/generic_sdram.c"
  66 #include "cpu/amd/dualcore/dualcore.c"
  67 #include "cpu/amd/car/post_cache_as_ram.c"
  68 #include "cpu/amd/model_fxx/init_cpus.c"
  69 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  70 #include "northbridge/amd/amdk8/early_ht.c"
  71
  72 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  73 {
  74         static const struct mem_controller cpu[] = {
  75                 {
  76                         .node_id = 0,
  77                         .f0 = PCI_DEV(0, 0x18, 0),
  78                         .f1 = PCI_DEV(0, 0x18, 1),
  79                         .f2 = PCI_DEV(0, 0x18, 2),
  80                         .f3 = PCI_DEV(0, 0x18, 3),
  81                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  82                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  83                 },
  84 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  85                 {
  86                         .node_id = 1,
  87                         .f0 = PCI_DEV(0, 0x19, 0),
  88                         .f1 = PCI_DEV(0, 0x19, 1),
  89                         .f2 = PCI_DEV(0, 0x19, 2),
  90                         .f3 = PCI_DEV(0, 0x19, 3),
  91                         .channel0 = { DIMM4, DIMM6, 0, 0 },
  92                         .channel1 = { DIMM5, DIMM7, 0, 0 },
  93                 },
  94 #endif
  95         };
  96
  97         int needs_reset;
  98
  99         if (!cpu_init_detectedx && boot_cpu()) {
 100                 /* Nothing special needs to be done to find bus 0 */
 101                 /* Allow the HT devices to be found */
 102
 103                 enumerate_ht_chain();
 104
 105                 amd8111_enable_rom();
 106         }
 107
 108         if (bist == 0) {
 109                 init_cpus(cpu_init_detectedx);
 110         }
 111
 112         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 113         uart_init();
 114         console_init();
 115
 116         /* Halt if there was a built in self test failure */
 117         report_bist_failure(bist);
 118
 119         setup_ibm_e326_resource_map();
 120
 121         needs_reset = setup_coherent_ht_domain();
 122
 123 #if CONFIG_LOGICAL_CPUS==1
 124         // It is said that we should start core1 after all core0 launched
 125         start_other_cores();
 126 #endif
 127         // automatically set that for you, but you might meet tight space
 128         needs_reset |= ht_setup_chains_x();
 129
 130         if (needs_reset) {
 131                 print_info("ht reset -\n");
 132                 soft_reset();
 133         }
 134
 135         enable_smbus();
 136
 137         memreset_setup();
 138         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 139
 140         post_cache_as_ram();
 141 }