src/mainboard/ibm/e326/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  30
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32
  33 static void memreset_setup(void)
  34 {
  35         if (is_cpu_pre_c0()) {
  36                 /* Set the memreset low */
  37                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  38                 /* Ensure the BIOS has control of the memory lines */
  39                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  40         } else {
  41                 /* Ensure the CPU has controll of the memory lines */
  42                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43         }
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48         if (is_cpu_pre_c0()) {
  49                 udelay(800);
  50                 /* Set memreset_high */
  51                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  52                 udelay(90);
  53         }
  54 }
  55
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58         /* nothing to do */
  59 }
  60
  61 static inline int spd_read_byte(unsigned device, unsigned address)
  62 {
  63         return smbus_read_byte(device, address);
  64 }
  65
  66
  67 #include "northbridge/amd/amdk8/raminit.c"
  68 #include "resourcemap.c"
  69 #include "northbridge/amd/amdk8/coherent_ht.c"
  70 #include "lib/generic_sdram.c"
  71
  72 #include "cpu/amd/dualcore/dualcore.c"
  73
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75
  76 #include "cpu/amd/model_fxx/init_cpus.c"
  77
  78 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  79 #include "northbridge/amd/amdk8/early_ht.c"
  80
  81 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  82 {
  83         static const struct mem_controller cpu[] = {
  84                 {
  85                         .node_id = 0,
  86                         .f0 = PCI_DEV(0, 0x18, 0),
  87                         .f1 = PCI_DEV(0, 0x18, 1),
  88                         .f2 = PCI_DEV(0, 0x18, 2),
  89                         .f3 = PCI_DEV(0, 0x18, 3),
  90                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
  91                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
  92                 },
  93 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  94                 {
  95                         .node_id = 1,
  96                         .f0 = PCI_DEV(0, 0x19, 0),
  97                         .f1 = PCI_DEV(0, 0x19, 1),
  98                         .f2 = PCI_DEV(0, 0x19, 2),
  99                         .f3 = PCI_DEV(0, 0x19, 3),
 100                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 101                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 102                 },
 103 #endif
 104         };
 105
 106         int needs_reset;
 107
 108         if (!cpu_init_detectedx && boot_cpu()) {
 109                 /* Nothing special needs to be done to find bus 0 */
 110                 /* Allow the HT devices to be found */
 111
 112                 enumerate_ht_chain();
 113
 114                 amd8111_enable_rom();
 115         }
 116
 117         if (bist == 0) {
 118                 init_cpus(cpu_init_detectedx);
 119         }
 120
 121         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 122         uart_init();
 123         console_init();
 124
 125         /* Halt if there was a built in self test failure */
 126         report_bist_failure(bist);
 127
 128         setup_ibm_e326_resource_map();
 129
 130         needs_reset = setup_coherent_ht_domain();
 131
 132 #if CONFIG_LOGICAL_CPUS==1
 133         // It is said that we should start core1 after all core0 launched
 134         start_other_cores();
 135 #endif
 136         // automatically set that for you, but you might meet tight space
 137         needs_reset |= ht_setup_chains_x();
 138
 139         if (needs_reset) {
 140                 print_info("ht reset -\n");
 141                 soft_reset();
 142         }
 143
 144         enable_smbus();
 145
 146         memreset_setup();
 147         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 148
 149         post_cache_as_ram();
 150
 151 }
 152